JP3440704B2 - Data transceiver and data transfer system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmitting / receiving apparatus and a data transfer system for transferring time stamped data via a network.

[0002]

2. Description of the Related Art As a method of transmitting data via a network, a synchronous communication method in which a transmitting side and a receiving side continuously transmit signals of the same cycle, and a fixed information of intermittent time intervals Asynchronous communication method that transmits units, and isochronous (Is
ochronous) transfer method. According to this isochronous transfer method, it is possible to secure a band in advance and perform highly real-time data transfer with guaranteed time delay.

This isochronous transfer system will be described with reference to FIG. This figure shows IEEE13
This is an example of the arrangement of packets on the bus in a system called the 94 high-speed serial bus. Three types of packets, a cycle start packet 101, an isochronous packet 102 and an asynchronous packet 103, are arranged on the network. . The broken line shows the first timing signal (cycle synch) that is the reference in this system, and the first timing signal is a signal of 125 μsec cycle (8 KHz).

The cycle start packet 101 is
This is a packet transmitted from a node called a cycle master among a plurality of nodes connected to this bus, and this cycle start packet 101 starts a new transmission cycle. The cycle master has a precise clock source and tries to transmit the cycle start packet 101 at the time interval of the first timing signal from this clock source, at which time the transfer of other packets is performed. Is in progress, the cycle start packet 10 is sent until the transfer is completed.
The transmission of 1 is delayed. Reference numeral 104 indicates this delay time (start delay), which is encoded in the cycle start packet 101 and sent to each node. It is guaranteed that the packet transmitted from the node will be received by another node within the same clock period.

Each node has a 32-bit cycle timer register. Each cycle timer register uses the lower 12 bits to count the clock signal of the system reference clock of 24.576 MHz (cycle 40.7 nsec) modulo 3072, and uses the upper 13 bits to count the 8 KHz reference signal. Cycles are counted, and seconds are counted by the most significant 7 bits. Then, the cycle master uses the cycle start packet 101 to copy the contents of its own cycle timer register to the cycle timer registers of all nodes, and synchronize all nodes within a certain phase difference. In this way, a common time reference is guaranteed in this network.

The isochronous packet 102 is a channel used to transfer data such as digital sound, video or performance data that requires precise timing reference. The isochronous packet 102 is always transmitted within each transmission cycle. Guaranteed to be done. Also, the asynchronous packet 1
Reference numeral 03 denotes a packet that is asynchronously transmitted when the transmission cycle of the isochronous packet 102 has a free time after the transmission of the isochronous packet 102 is completed.

Now, when transmitting time series data such as voice data, image data or performance data using these various networks, when the transmission path is not a perfect synchronous communication system, it is transmitted. In order to guarantee the reproducibility of the data on the time axis, the data itself is sent with a time stamp indicating the time at which the data should be reproduced, and the receiving side refers to the time stamp and refers to that time. The data is reproduced when the data reaches the point.

[0008]

The time stamp used on such a network must be capable of uniquely recognizing time. In other words, the time stamp requires a repetition period of a time width that is considered to be reasonable to some extent, and thus requires a large amount of information. When information is represented by digital representation, a large amount of information corresponds to a large number of bits. Therefore, in order to increase the time resolution of time information specified by a time stamp, a large amount of information, that is, a large number of bits. Will be required. For example,
In the case described with reference to FIG. 7, a 32-bit time stamp is used.

Further, in the transmission system of the type in which data is transmitted with the time stamp added as described above,
In addition to data, it is necessary to send time stamp information at predetermined time intervals, and it is desirable that the ratio of time stamp information to transmission data is small. However, as described above, in order to ensure the uniqueness of the time expressed by the time stamp and to improve the time resolution, the number of bits of the time stamp becomes large, and the data transfer efficiency decreases. There was a point.

Therefore, according to the present invention, the number of bits of the time stamp is set in the data transfer system in which the time stamp is added to the data and the data is transmitted so that the data to be transmitted can be reproduced on the time axis. The purpose is to improve the data transfer efficiency by reducing.

[0011]

In order to achieve the above-mentioned object, a data transmitting apparatus of the present invention has a common cycle.
Data based on signals generated according to common time standards
The common time between each node that is transmitted and connected
In a network where the reference is guaranteed, there is provided a data transmitting apparatus for exiting feed the transmission data to which the time stamp is added, the time stamp, consisting of the predetermined period
When the data is represented by the data indicating the relative time position within one cycle of the time reference , and has a buffer and consists of the predetermined cycle.
The transmission data is written in the buffer on the basis of the interval reference, and the transmission data is taken out from the buffer on the basis of the signal generated according to the time reference and transmitted on the network.

Further, the data receiving apparatus of the present invention uses a signal generated according to a common time reference having a predetermined cycle.
Data transmission is performed based on the
In a network where the common time base is guaranteed
Te, wherein a data receiving apparatus for receiving data which represented the time stamp is added by the data indicating the relative time position within one period of the time reference of a predetermined period, a buffer, The data received from the network is written in the buffer based on the signal generated according to the time reference , the data is taken out from the buffer based on the time reference having the predetermined period , and the predetermined cycle is set.
The data is reproduced on the time axis based on a time reference consisting of a period and the time stamp added to the extracted data.

Further, the data transfer system of the present invention is
And a data transmitting node and a data receiving node, the transfer of data is controlled based on the signal that will be generated in accordance with a common time reference having a predetermined period, the connection to the network
In the data transfer system in which the common time reference is guaranteed between the respective nodes , the data transmission node comprises:
A time stamp represented by data indicating a relative time position within one cycle of the time reference having the predetermined cycle is added to the transmission data, and the transmission data to which the time stamp is added is set as the time reference having the predetermined cycle. Is written to the first buffer based on the
The transmission data is taken out from the first buffer based on a signal and transmitted to the network, and the data reception is performed.
Node writes the data transmitted on said network on the basis of a signal generated in accordance with the time reference in a second buffer, or the second buffer, based on the time reference consisting of the predetermined period La Defense Take out the data
The data is reproduced on the time axis based on a time reference having a predetermined period and the time stamp added to the extracted data.

[0014]

1 is a block diagram showing an example of the configuration of a data transfer system of the present invention. In the figure, reference numeral 10 denotes the network, which can perform the isochronous transfer shown in FIG. Further, 11 to 13 are examples of each node connected to the network 10, and 12 is a transmitting station that transmits time series data that needs to be reproduced on the time axis, such as a tone waveform signal. Is a sound source device for sending out. Further, 13 is a receiving station for receiving the time series data,
For example, a mixer that mixes the tone waveform signals. Time-series data such as musical tone waveform data sampled at a predetermined sampling timing is transmitted from the transmitting station 12 with a time stamp added, and the receiving station 13 receives the data and receives the timing designated by the time stamp. Play the tone waveform data with. A plurality of other nodes are also connected to the network 10, and the other station 11 is the cycle master (cycle start packet transmitting station) described above.

FIG. 2 is a block diagram showing an example of the internal configuration of each of the nodes 11 to 13, 21 is a central processing unit (CPU), 22 is a ROM in which operation programs and various data are stored, and 23 is. A RAM used as a working area or the like, 24 includes the cycle timer register, a timer for generating various timing signals, 26 is a network interface circuit for connecting to the network 10, and 27 is an internal bus. Also, 25
Is a data use / generation circuit, and this node is the transmitting station 1.
When it is 2, it is a data generation circuit, and when it is the receiving station 13, it is a data utilization circuit.

FIG. 3 is a functional block diagram for explaining the data transfer operation in the transmitting station 12 and the receiving station 13. FIG. 3A is a block diagram showing the function of the transmitting station 12. In this figure, reference numeral 31 is a data generation circuit, which uses isochronous channels by data consisting of a plurality of musical sound samples sampled at a predetermined sampling period for each reference period of 125 μsec and a time stamp added to the data. To generate a packet to be transmitted. 32 is a data buffer for storing the packet generated by the data generation circuit 31;
Reference numeral 33 denotes a FIFO (First In First Out) standby buffer in which the packet stored in the data buffer 32 is written according to the output (cycle timer output) from the cycle timer register indicating the first timing, and 34 denotes A transmission buffer that stores the packet read from the standby buffer 33 in response to a cycle start signal generated by receiving a cycle start packet indicating the start of the new transmission cycle. The packet stored in is transmitted to the network 10 at the timing designated by the isochronous channel.

FIG. 3B is a functional block diagram of the receiving station, and 35 is a receiving buffer for receiving and storing a packet to be received by this receiving station among the packets transmitted on the network, 36. Is a standby buffer having a FIFO structure in which the packet stored in the reception buffer 35 is written in response to the cycle start signal,
7 is a data buffer for reading the packet in the standby buffer 36 according to the output of the cycle timer indicating the first timing, 38 is the data transmitted by the packet stored in the data buffer 37 designated by a time stamp. It is a data utilization circuit that reproduces at different timings.

As described above, on the transmitting side, the data packet is generated in correspondence with the first timing and is transmitted to the network by the cycle start signal (second timing). On the other hand, on the receiving side, the packet transmitted according to the second timing is received,
The data is reproduced according to the first timing.

FIG. 4 is a diagram for explaining a transmission packet generated in the data generating circuit 31. Figure 4
(A) is a diagram for explaining the data to be transmitted. For example, a continuous signal such as a tone waveform signal has a predetermined sampling interval ts (ts = 25 (= 125 in this case).
Five discrete data 1 to 5 obtained by sampling at / 5) μsec) are data to be transmitted. The first sampling data 1 is data sampled at a time point delayed by the time t from the first timing signal, and other sampling data 2 to
Data 5 is sampled at a timing delayed from the time t by a time corresponding to a corresponding multiple of the time ts.

In this bus system, the system reference clock frequency Φ = 24.576 MHz (clock cycle = 40.7 ns), and the time position within the one reference cycle (125 μsec) is the unit of the clock cycle. Can be expressed as That is, the above 1
The time position in the reference cycle can be represented by 0 to 3071 clocks with the clock cycle as a unit.

Therefore, in the present invention, as the time stamp, a time stamp value is a value representing the time position t of the first sampling data 1 in the reference cycle in the reference cycle in units of the clock cycle. For the other sampling data 2 to 5, the reproduction time is determined by sequentially adding the sampling cycle ts from the first sampling data 1.

The structure of a packet for transmitting such data is shown in FIG. 4 (b). As shown in this figure,
The transmission packet is configured by first combining the time stamp indicating the time t, and then combining the first to fifth sampling values. As described above, the time stamp represents the time t in the reference cycle by the number of system clocks, and takes a value of 0 to 3071, so that it becomes 12-bit data.

For comparison, the structure of the conventionally used time stamp is shown in FIG. 4 (c). Also in this case, the packet is composed of a time stamp and each sampling data 1 to 5 similarly to the packet of the present invention shown in (b), but the time stamp is, for example, 32-bit data. That is, the lower 12 bits indicate the time t as in the case of the present invention, the next 13 bits indicate the reference cycle number, and the uppermost 7 bits indicate the time expressed in seconds. . As described above, since the time stamp is conventionally expressed as all the absolute time shared by each node, the time stamp is 20 bits longer than the packet of the present invention shown in (b) above.

In the network system of the present invention, the transmission data generated according to the first timing is sent to the network according to the second timing, but as described above, the second timing is used. May be generated with a delay with respect to the first timing, and therefore one reference cycle determined by the first timing may include two transmission data. . Even in such a case, the data transfer system of the present invention can reproduce the original data at a predetermined time position without any problem.

The operation of the data transfer system of the present invention will be described with reference to the time chart of FIG. In this figure, the horizontal axis is the time axis, and the data obtained by sampling the original data in the reference cycle from time t1 to t2 is added with the above-mentioned 12-bit time stamp in the data generation circuit 31. Packet 51 and stored in the data buffer 32. The packet 51 stored in this data buffer 51 is output by the cycle timer generated at time t2, and the FI
It is stored in the standby buffer 33 having the FO structure.

Further, the packet 52 corresponding to the original data in the period from time t2 to t3 is similarly generated and stored in the data buffer 32. At time t3, the output of the cycle timer causes the packet 52 to be stored in the standby buffer 33. As described above, at this time t3, since the cycle start packet is not transmitted, the packet 51 is stored in the standby buffer 33.
And a packet 52 are stored. Here, as shown in the figure, when a transmission cycle is started with a slight delay from the time t3 and a cycle start packet is transmitted, a cycle start signal is output, and in response thereto, the packet 51 from the standby buffer 33 is output. Are transferred to the transmission buffer 34. The packet stored in the transmission buffer 34 will be transmitted to the network 10 at the time corresponding to this isochronous channel in this transmission cycle.

In the illustrated case, this transmission cycle is started later than the reference cycle, and the packet 51 is sent out on the network after the next reference timing time t4. At this time, this packet will be stored in the reception buffer 35 after time t4. Then, when the next transmission cycle is started at a timing later than the time t4 by the time td and the cycle start packet 101 is sent out, the packet 52 is transferred from the standby buffer 33.
Are transferred to the transmission buffer 34 and sent out on the network during this transmission cycle. In this way, two packets are transmitted / received within one reference cycle from time t4 to time t5.

Packets 51 and 52 are received and written in the reception buffer 35 during the period from time t4 to time t5. The received packet is transferred to the standby buffer 36 by the cycle start signal and indicates the reference timing. By the output of the cycle timer, the standby buffer 3
6 to the data buffer 37. That is, after the time t4, the packet 51 is stored in the reception buffer 35, and the packet 51 is stored in the standby buffer 36 by the cycle start signal indicating the start of the next transmission cycle. The packet 52 transmitted in the transmission cycle started by this cycle start signal is stored in the reception buffer 35. At time t5, the output of the cycle timer causes the packet 51 stored in the standby buffer 36 to be written in the data buffer 51 and, as described above, reproduced on the time axis in the data utilization circuit 38. The packet 35 stored in the reception buffer 35 is transferred to the standby buffer 36 in response to a cycle start signal indicating the start of the next transmission cycle, and written in the data buffer 37 at time t6. , Will be reproduced with accurate timing during the period from time t6 to time t7.

In this way, it is possible to reproduce the original data at an accurate timing only by using the time stamp data having a small number of bits, which represents only the time difference from the cycle timer time in each reference cycle. Become.

The function of each functional block described above can be realized by software. FIG. 6 is a flowchart of processing on the transmitting side and the receiving side for realizing such a function. In this figure,
(A) shows the processing on the transmitting side, and (b) shows the processing on the receiving side. On the sending side, step S
Reference numeral 10 is the data generation process. This process realizes the same function as that of the data generation circuit, and is a process of inputting the original data to be transmitted and generating a data packet to which a time stamp corresponding to the start value is added.

Step S12 is a cycle timer interrupt process which is executed when the cycle timer interrupt indicating the first timing occurs. Data in the data buffer is added to the standby buffer and erased from the data buffer. Processing is performed. Step S14 is a cycle start interrupt process started by a cycle start interrupt generated when the cycle start packet is received. In this process, the process of extracting the oldest data in the standby buffer to the transmission buffer is performed. Done.

(B) shows the processing on the receiving side, and step S20 is the data reception interrupt processing that occurs when a packet on the network is received. In this processing, the received data is necessary for the own station. When the data is
Record the packet in the receive buffer. Step S2
1 is a process started by a cycle start interrupt generated when the cycle start packet is received. The packet recorded in the reception buffer is added to the standby buffer and the packet is deleted from the reception buffer. It is a process to do. Step S24 is a process started by the cycle timer interrupt and is a process of moving the oldest data in the standby buffer to the data buffer.

In the above description, IEEE1394
The case of using the high-speed serial bus system has been described, but the present invention is not limited to this, and can be similarly applied to a network system that supports similar isochronous transfer. Also, the number of bits of the time stamp can be arbitrarily determined according to the required time accuracy and the like. Furthermore, the data to be transferred is not limited to musical tones, but may be, for example, image (moving image) data,
Any waveform data such as waveform data other than musical sound may be used.

[0034]

As described above, according to the present invention,
The number of bits of the time stamp can be reduced, and the transmission efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing an outline of a data transfer system of the present invention.

FIG. 2 is a diagram showing a configuration of each station in the data transfer system of the present invention.

FIG. 3 is a functional block diagram for explaining a transmitter and a receiver in the data transfer system of the present invention.

FIG. 4 is a diagram for explaining a packet in the present invention.

FIG. 5 is a timing chart for explaining the operation of the present invention.

FIG. 6 is a flowchart of processing in the data transfer system of the present invention.

FIG. 7 is a diagram for explaining a packet on the network.

[Explanation of symbols]

10 networks, 11 nodes, 12 transmitting stations, 1
3 Receiving station, 21 CPU, 22 ROM, 23 RA
M, 24 timer, 25 data use / generation circuit, 26
Network interface circuit, 27 internal bus,
31 data generation circuit, 32, 37 data buffer,
33, 36 standby buffer, 34 transmission buffer, 35
Reception buffer, 38 data utilization circuit, 51, 52,
102 isochronous packet, 101 cycle start packet, 103 asynchronous packet, 104 delay time

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasushi Otani 10-1 Nakazawa-cho, Hamamatsu-shi, Shizuoka Yamaha Stock Company (72) Inventor Tatsutoshi Abe 10-1 Nakazawa-cho, Hamamatsu-shi, Shizuoka Yamaha Stock Company (56) Reference JP-A-3-133233 (JP, A) JP-A-9-298558 (JP, A) JP-A-9-186699 (JP, A) JP-A-8-97807 (JP, A) JP-A-3-226144 (JP, A) JP-A-10-107851 (JP, A) JP-A-63-306740 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 12/56 H04L 25/00

Claims (3)

(57) [Claims] 1. According to a common time reference having a predetermined period.
Data is transmitted based on the signal generated by
The common time base is guaranteed between each successive node
In the network, a data transmitting apparatus for exiting feed the transmission data to which the time stamp is added, the data indicating the relative time position of the time stamp, the one cycle of the composed time reference <br/> a predetermined period And has a buffer, writes the transmission data to the buffer based on a time reference consisting of the predetermined cycle, and extracts the transmission data from the buffer based on a signal generated according to the time reference. A data transmission device characterized by transmitting the data over a network. 2. According to a common time reference having a predetermined period.
Data is transmitted based on the signal generated by
The common time base is guaranteed between each successive node
In the network, a data receiving apparatus for receiving data that the timestamp represented by data is added to indicate the relative time position of the predetermined cycle consisting of time reference <br/> 1 cycle of A buffer, and the data received from the network is used as the time reference.
According written into said buffer based on the signals generated by, on the basis of the time reference of a predetermined period retrieves data from the buffer, the time that the added to the retrieved said a time reference having a predetermined period data A data receiving device characterized in that the data is reproduced on a time axis based on a stamp. 3. and a data transmitting node and a data receiving node, the data on the basis of the signal that will be generated in accordance with a common time reference having a predetermined periodic transfer is controlled, network
The common time reference between the nodes connected to the network
There a data transfer system that is guaranteed, the data transmitting node, the time group consisting of the predetermined cycle
A time stamp represented by data indicating a relative time position within one quasi period is added to the transmission data, and the transmission data with the time stamp is formed of the predetermined period.
Writing the first buffer based on the time reference, the time
The transmission data is taken out from the first buffer based on a signal generated according to the time reference and transmitted to the network, and the data receiving node is generated according to the time reference.
Writing the data transmitted on said network on the basis of a signal to the second buffer, it from the predetermined cycle
That time removed La Defense over data or said second buffer based on the reference, the data on the time axis on the basis of the said time stamp appended to the data retrieved said time reference having a predetermined cycle A data transfer system characterized by reproduction.