JPS62141694A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent the malfunction of an address buffer by inhibiting an address signal from changing while a current is changing due to the transitional action of an output buffer and maintaining the previous address signal. CONSTITUTION:The titled device has an ouptut change detection circuit 8 detecting a change in an output when stored data is read out, and an address change inhibiting circuit 9 receiving the output of said output change detection circuit 8. Pulse width is set according to the values of capacitances C1, C2, C3 and C4 so that said width can be the same as the time showing a transitional action by receiving a change in the output signal of a sense amplifier 6, and therefore the output change detection circuit 8 outputs a signal CL at a low during said period and its inverse signal CL which becomes high while an instan taneous voltage drops appears. Receiving the output signal CL and the inverse of CL from the output change detection circuit, the address change inhibition circuit 9 does not operate a clock inverter 18. While the inverse signal CL is at a high level, the gate of a clock inverter 16 is opened. Therefore, the address signal is separated from the row and column decoders and the address buffer, and data held by an inverter 17 and the clock inverter 18 is transmitted to the row and column decoders.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor memory device that reads data stored in the memory device using an address signal. In a semiconductor memory device that reads data stored in the storage device using a signal, when the output changes excessively when reading the stored data, the change of the address signal is prohibited and the previous address signal is held. This is to prevent malfunction of the address buffer due to current changes during transient operation of the output buffer.

[Conventional technology]

Semiconductor memory 1: alpha device for reading data stored in a memory device d using a conventional address signal In the case of a semiconductor device, a part of the address signal causes a row decoder to select a word line of a memory cell array, as shown in FIG. Then, the column decoder and column gate select a bit line based on the remaining address signal, thereby selecting the memory cell corresponding to the input address signal from among the memory cells in the memory cell array.

The structure was such that the data in the memory cell was increased and solidified, and the cardinal IIIE II capability was increased and outputted through the output buffer.

[Problem that the invention seeks to solve]

However, in the conventional configuration, when the address signal changes and the output to be read changes from low to no, a transient current change occurs due to the output buffer having a large drive capacity, and the output buffer's Il ! Since an instantaneous drop in the first position appears on the source wiring, the address buffer's NO output signal drops instantaneously, causing a malfunction in which it is determined to be a low signal. In addition, when the output to be read changes from no to low, a relatively large current flows through the ground potential line of the circuit and the ground potential rises, causing the logic threshold of the transistor forming the address buffer to rise. There was a problem in that the voltage 251 became substantially high and the address signal of 1 was judged to be low, resulting in a malfunction. Therefore, in order to solve these conventional problems, the present invention provides a semiconductor memory device that does not affect the output of the address buffer even if the output signal of the output buffer changes and a transient current change occurs. The purpose is to obtain.

[Means to solve the problem]

The semiconductor memory device of the present invention includes: (a) when reading data stored in the memory device using an address signal; (b) an output change detection circuit that detects a change in output when reading stored data t- and.

(c) The device is characterized by comprising an address change prohibition circuit which receives the output of the output change detection circuit and prohibits the address signal from changing while the output is changing and retains the previous address signal. semiconductor storage device.

[Effect]

According to the above structure of the present invention, when reading data stored in a semiconductor memory device, the output change detection circuit detects a '4-style transient change during rising and falling operations of the output of the output buffer. The address change prohibition circuit detects the period in which an instantaneous voltage drop in the power supply voltage appears, and the address change prohibition circuit detects the period in which the output signal of the output change detection circuit is applied (the address signal is prohibited from changing). The previous address signal is retained.Therefore, according to the present invention, it is possible to prevent the address buffer from malfunctioning while the output buffer exhibits transient operation.

〔Example〕

Hereinafter, the present invention will be described in detail based on examples.

FIG. 1 shows a configuration q of an inventive semiconductor memory device. In the figure, 1 is an address buffer, 2.5 is a row decoder and a column decoder that convert an address signal into a signal for selecting a memory cell corresponding to the address signal, 4 is a memory array in which memory cells are arranged, and 5 is a A column select selects a memory cell corresponding to a signal from the column decoder from among the memory cells selected by the row decoder, 6 a sense amplifier that amplifies data in the memory cell, 7 an output buffer for increasing *a capacity, 8 is an output change detection circuit that detects a change in the data output to be read, and 9 is an address change prohibition circuit that prohibits a change in the address signal based on a signal from the output change injection circuit 8.

The basic structure of the output change production circuit 8 will be explained with reference to FIG. 11.12 is a delay inversion circuit, and the delay time can be arbitrarily determined by each number C1, C2, C3, and 04. L3 and 14 are two-person negative AND gates, and when all inputs are low, the output is NO. By connecting the output signal to be read and the output signal of the delay inversion circuit 11 to the negative AND gate 13, a signal that becomes high when the two signals are low, that is, when the output signal to be read falls, is obtained.

On the other hand, by connecting the output of the inverter 10, that is, the negation of the output signal to be read and the output signal of the delay inversion circuit 14 to the negative AND gate 14, the output signal to be read rises. You can get the word. By connecting the output signal of negative AND gate 15.14 to the tour gate, the output signal to be read becomes a signal O that becomes low when it rises or falls.
L is obtained, and an output signal read out by passing through an inverter can be obtained as a signal τ which becomes no when it rises or when it falls. Here, one pulse of the OL signal and the τT signal can be determined by the values of the capacitances C1, C2, C3 and C4, and the pulse width is determined by the pulse width when the output buffer performs transient operation in response to changes in the output signal of the sense amplifier. By setting the time to be the same as the time at which an instantaneous voltage drop in the power supply wiring appears due to a transient change in the t current, the OL multiplication signal is This is the signal that represents the instantaneous voltage drop, and τ is the tm that represents the instantaneous voltage drop.
Yugo gets high. @Figure 4 is a time chart showing the signal waveforms of each part in Figure 3.

FIG. 5 shows a detailed configuration of the address change prohibition circuit 9.

Address change prohibition circuit is clocked inverter 16.1
8 and an inverter 17,
It receives the output signals OL, m of the output change inhibiting circuit. O
When the L signal is high, that is, while the output buffer does not perform any transient operation and maintains a high or low level output, the clocked inverter 18 does not operate, and the address signal is transmitted between the clocked inverter 16 and the output buffer. The signal is sent to the row decoder and column decoder via the inverter 17.

On the other hand, when the OL double signal is high, that is, when a change in current due to a transient operation of the output sofa appears, the gate of the clocked inverter 16 is open, so the address buffer, row decoder, and column decoder are separated. Data held by the inverter 17 and clocked inverter 18 is sent to the row decoder and column decoder.

Therefore, in this embodiment, two sets of delay inverting circuits and two negative AND gates detect changes in the readout output, and a master type latch inhibits changes in the address signal to create an output buffer. to 2
Address buffer for 1st work! @Preventing operation.

〔Effect of the invention〕

As explained above, the present invention prevents the address signal from changing while a transient current change occurs due to the transient operation of the output cover sofa, and maintains the previous address No. 9, thereby preventing the transient current from changing. 1 due to change! It is possible to prevent apparent malfunctions of the address buffer caused by instantaneous voltage drops in the source wiring.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor memory device of the present invention, FIG. 2 is a block diagram of a conventional semiconductor memory device, FIG. 3 is a circuit diagram of an output change detection circuit of the present invention, and FIG. 4 is a circuit diagram of an output change detection circuit. FIG. 5, which shows a time chart of , is an address change prohibition circuit diagram of the present invention. 1... Address buffer 2... Row decoder 3... Column decoder 6... Sense amplifier 7... Output buffer 8... Output change detection circuit 9... Address change inhibition circuit 11.12.・Delay inversion circuit 13.14 ・Negative AND gate 16.18・
...Clock Toy/Bark Noboru 1 Figure Sumire 212 Tomoe Power Converter Fk Tagura 31B Shichikasu 4 Shiya Nine Tomoe 1B Tomoe's Taimira 2゛° Now Yard 葆 41] Ko'TP' Cis Nitride Back Stop 1 koji written note 5 days

Claims (1)

[Scope of Claims] (a) When reading data stored in a storage device using an address signal, (b) An output change detection circuit that detects an output change when reading stored data; (c) A semiconductor memory comprising an address change prohibition circuit which receives the output of the output change detection circuit, prohibits the address signal from changing while the output is changing, and retains the previous address signal. Device.