JPS62140528A - Time division multiplexing signal separation system - Google Patents

Abstract

PURPOSE:To decrease the generation of a shock by executing stop of detection of a dummy signal, or initialization of either a write address or a read-out address of a storage device, when a read-out clock frequency is being controlled. CONSTITUTION:In a read/write address counter relative difference detecting circuit 22, a relative difference of a write address signal WA and a readout address signal RA is detected, and when it goes to a prescribed difference before the write address signal WA and the read-out address signal RA are superposed, a write address counter 16 and a read-out address counter 21 are initialized, and the generation of a long burst error can be evaded. In case a dummy flag bit is lost and a read-out clock frequency control cannot be executed, a dummy signal is written in a frame memory 17-1, and also, in case the read-out clock frequency control cannot be executed, in case of demodulation, shock noise is generated. In such a case, when a PN signal is applied as a dummy data, even if the dummy data is demodulated, the level goes to zero, the shock noise can be evaded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is a method for multiplexing multiplexed signals obtained by time-division multiplexing a plurality of digital or analog information signals having different sampling frequencies or clock signal frequencies. The present invention relates to a time division multiplexing signal separation method for separating previous original information signals.

(Background of the Invention) In the time-division multiplexing signal separation method as described above, N-channel information signals having mutually different sampling frequencies or clock signal frequencies are transferred to the highest frequency of the sampling frequency or clock signal frequency, or to the highest frequency of the sampling frequency or clock signal frequency. Time-division multiplexing is performed using a reference clock signal obtained by multiplying the above frequency by N, and a gummy signal is sent to the part where the information signal is insufficient. On the receiving side, after detecting the dummy data, the dummy signal is read out without being written to the storage device. proposed a time-division multiplex signal separation method in which the original information signal is separated by lowering the signal level (Japanese Patent Application No. 6O-114355).

In this time-division multiplex signal separation method, the read clock frequency control of the storage device is inserted in pairs with a dummy signal, and while detecting 7 lag bits of the dummy signal, the information signal between one frame (corresponding to the dummy signal) is The write address counter is held without being incremented without being written to the storage device. At the same time, the read clock frequency of the storage device is lowered to return to the relative address relationship before the read/write relative address detection circuit started the read clock frequency control, and then the read clock frequency control of the storage device is ended.

(Problems to be Solved by the Invention) In the conventional time division multiplexing/demultiplexing system as described above, when a dummy flag bit is generated on the time division multiplexing side, data is transmitted in the transmission system and/or time division multiplexing system. If an error occurs and the termie flag pit is reversed, a malfunction will occur. This example would look like this: Even though the time division multiplexing side does not output dummy flag bits, the time division multiplexing side accidentally outputs dummy flag pits (
This may be the case when a dummy flag bit (pseudo dummy flag pit) is detected, or conversely, a dummy flag bit is output on the time division multiplexing side but cannot be detected on the time division multiplexing/demultiplexing side.

In other words, if a pseudo dummy flag pit occurs during read clock frequency control and read clock frequency control is started again, the read address will overtake the write address of the storage device, and the read and write operations of the storage device will continue for a long period of time. Due to the overlap, a long burst error occurs, it takes a long time to return to correct memory operation, and a long shock noise occurs when demodulating.

Additionally, if a pseudo dummy flag pit occurs while the read clock frequency control is stopped and the read clock frequency control is started, writing to the storage device will be stopped and the read data will be missing one frame. , there is a problem that demodulation causes t waveform distortion.

SUMMARY OF THE INVENTION An object of the present invention is to minimize the above-mentioned problems, reduce the occurrence of shocks, and provide a nine-time division multiplex signal separation system.

(Elaborate Means for Solving the Problems) The present invention provides N-channel information signals having mutually different sampling frequencies and clock signal frequencies at the highest frequency of the sampling frequency or clock signal frequency, or at the highest frequency. Time division multiplexing is performed using a reference clock signal obtained by multiplying the above frequency by N, a dummy signal is inserted into the part where the information signal is insufficient, the 9 time division multiplexed signal is received, the dummy signal is detected, and the dummy signal is stored in the storage device. In a time division multiplexed signal separation method in which an information signal is read out from a storage device by performing read clock frequency control that temporarily reduces the read signal frequency without writing data to the storage device and restores the original signal, during read clock frequency control,
At least one of stopping the detection of the dummy signal or detecting the relative difference between the write address and the read address of the storage device and initializing the write address and the read address before the two addresses overlap. I made it possible to do so.

(Function) In the present invention configured as described above, detection of dummy data is stopped during read clock frequency control, so even if an error occurs in the dummy flag bit and a pseudo dummy flag pit occurs, a pseudo dummy flag pit is generated. Due to the dummy flag bit, read clock frequency control is not started again.

Further, a relative difference between a write address and a read address of the storage device is detected, and the write address and read address are initialized before the two addresses overlap. Therefore, a pseudo dummy flag bit is generated and the read address does not overtake the write address of the storage device.

(Example of the invention) The present invention will be explained below using examples.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In this embodiment, for example, a multiplexed signal obtained by QPSK demodulating the audio subcarrier of satellite broadcasting and multiplexing the resulting 2048 Mbtt/S bit stream by N (=4) channels according to the above-mentioned nine methods will be described. The example shows the case of separation.

The frame structure of this pit stream is as shown in FIG. That is, 16-bit frame synchronization data, 8-bit dummy information, 2032-bit A channel information signal, 8-bit dummy information, 2032-bit B channel information signal, 8-bit dummy information, 2
032-bit C channel information signal, 8-bit dummy information, 2032-bit D channel information signal,
A unit frame sequence is formed by adding up the remaining 16 bits. The dummy information before the information signal of each channel includes a dummy flag bit indicating whether the information signal of the following channel is dummy data. By checking this dummy flag bit, it is determined whether the information signal of the following channel is dummy data or not.

A time division multiplexed signal obtained by the above-described time division multiplexing method is input to the input terminal 10. In this embodiment, a 4.times.20482O48/80 bit stream is input to the input terminal 10.

This bit stream is transmitted to the 7-rem synchronization signal detection circuit 11.
The frame synchronization signal detection circuit 11 detects the frame synchronization signal, and the clock signal reproduction circuit 12 reproduces the write clock signal wcK. Further, the pit stream and the write a check signal Wc3 are supplied to the dummy flag bit detection circuit 13, which detects the dummy flag bit in the dummy information and determines whether or not the information signal of the following channel is dummy data. When it is determined that there is a write address counter 16, a prohibition instruction signal W48 for prohibiting counting by a write address counter 16, which will be described later, is output.

The frame synchronization signal, the write a-check signal W0, the output of the channel selection instruction switch 14 for selecting a receiving channel, and the read clock signal RcK (to be described later) are supplied to the system timing generation circuit 15, and the system timing generation circuit 15 outputs the time division multiplexed signal. Separation device (hereinafter referred to as
(also referred to as a decoder) generates timing signals necessary for the decoding action by the main body M.

On the other hand, in this embodiment, four frame memories O', ~M
F'4) configuration buffer frame memory 17-1, frame memory changeover switches 17-2 and 17-4,
Frame memory selector switch 1 from pit stream
A memory block 17 is provided, comprising an input selection switch 17-3 which is selected by the channel selection instruction switch 14 and supplies information signals of nine channels to 7-2. Here, the capacity is set to be able to store data transmission of one frame memory Fil frame: jt (2032 bits in this example).

The write clock signal WcK is supplied to the write address counter 16 to generate a friend frame memory number signal WF corresponding to the write address signal WA and the write frame memory number. The write address signal WA is supplied to the memory block 17 to specify the write address, and the frame memory number signal WF is supplied to the changeover switch 17-2.
control to select the write frame. On the other hand, the inhibit instruction signal WXNII is also supplied to the write address counter 16, and the advance of the address signal is stopped by the inhibit instruction signal Wx□, thereby inhibiting the write operation for one frame memory in the memory block 17.

The write clock signal w is supplied to the 9-frequency divider circuit 18 and frequency-divided to have a frequency (=f) that is 1/N of the transmission a-clock signal frequency after time division multiplexing. The output signal of the frequency dividing circuit 18 is supplied to a read clock frequency control circuit 19,
The read clock frequency control circuit 19 controls the frequency f.
. The read a-clock frequency control circuit 19 outputs the dummy flag detection output DMF when the dummy flag is detected by the dummy flag bit detection circuit 13 and the output of the frequency dividing circuit 18. In response, the read clock signal frequency f is gradually lowered from the frequency f to the frequency f from the time of writing to the specific frame memory of the memory block 17, for example, the first frame memory W, after the dummy flag is detected. If a difference of, for example, two frames is detected between the addresses written into the first frame memory E and those read from the first frame memory E, the read/write relative address detection circuit 20
The configuration is such that the output frequency is increased from frequency f3 to frequency f.

Furthermore, during the read clock frequency control described above, the read clock frequency control circuit 19 sends a frequency control state signal 5TA to the dummy flag pit detection circuit 13.
The configuration is such that the operation of the dummy flag pit detection circuit 13 is prohibited by supplying TE.

The read clock signal RCx is supplied to the read address counter 21, and the read address counter 21 generates a read address signal RA and a frame memory number signal RF corresponding to the read frame memory number.

The read address signal RA is supplied to the memory block 17 to designate a read address, and the frame memory number signal RF controls the changeover switch 17-4 to select a read frame.

From the IJ-me (pits supplied to the input terminal 10),
A multiplexed transmission lock signal, that is, a write clock signal WCK, and a frame synchronization signal are detected, and frame synchronization is performed.

In addition, according to the timing signal from the system timing generation circuit 15, a delay of one frame is provided between the write frame memory and the read frame memory when the power is turned on and when the selected channel is switched by the channel selection instruction switch 14. That is, the changeover switches 17-2 and 17-4 are initialized so as to have an offset of two frames, which is one frame, between the write frame memory and the read frame memory.

On the other hand, the address signal WA from the write address counter 16 and the address signal RA of the read address counter 21 color are supplied to the address counter relative difference detection circuit 22 to detect the read/write address before the read address and write address overlap. Detect the counter relative difference,
According to the address relative difference detection signal ADxNT, the write address counter 16 and the read address counter 16 and
This is to initialize the register 21.

Suppose channel B is now channel selection instruction switch 1.
4, and the sampling frequency or clock signal frequency of the B channel is lower than that of other channels before multiplexing on the transmitting side.

After frame synchronization is established, input selection switch 1 is activated by a timing signal from system timing generation circuit 15.
7-3, the B channel information signal is extracted from the pit stream, and the frame memory number signal W
By switching the changeover switch 17-2 by F, information signals for one channel are sequentially supplied to one frame memory, and are sent to the frame memories E1, MF'2, . . . -IF4, in synchronization with the write clock signal WcK. IF, ,...
・Written to sequentially.

On the other hand, the write clock signal WcK is divided by N by 6% in the frequency divider circuit 18 and the read clock frequency control circuit 19
A read clock signal RcK having a frequency f (=fw/4) is outputted from the circuit. Further, the frame changeover switch 17-4 is switched by the frame memory number signal RF to be switched two frames behind the write frame memory and in synchronization with the read clock signal Rc, so that the frame memories g1, . . . -IF4, . The B channel information signals stored from .

However, it is assumed that dummy data DU is now inserted in the 100th B channel. In comparison, a dummy flag pit indicating that the next information signal is dummy data is set up in the dummy information immediately before the B channel in the 11th frame of the 100th frame, and this dummy flag bit is a dummy flag bit. It is detected by the flag pit detection circuit 13, and a prohibition instruction signal - is output. FIG. 3 shows the frequency change of the read clock signal R6K. In FIG. 3, DU schematically shows the detection of a dummy flag pit, and the dummy flag pit is detected and f'Lt time is 1. It is shown at (16, 11,).

When this dummy flag pit is detected, a prohibition instruction signal W48 is output, and writing of the B channel information signal (dummy data in this case) for one frame is stopped. In addition, the prohibition instruction signals W and NH are output, the count value of the write address counter 16 is stopped for one frame, and the information of the B channel next to the dummy data is written on the one frame memory where the dummy data is temporarily stored. , writing of the B channel information signal (dummy data in this case) for one frame may be substantially prohibited.

Therefore, the data written to the frame memory is only the information signal of the 7'tB channel, excluding dummy data. However, during this time, readout is performed in synchronization with readout clock signals Rc and K having the same frequency f. As a result, the interval between the read frame memory and the write frame memory becomes closer, and at time t when writing is restarted, the read frame memory is in a state where it is in the frame next to the write frame memory. Even in this state, writing to each frame memory MF1, . . . -MF4, . . . is performed sequentially. During this period, the first time data is written to the first frame memory V after the dummy flag bit is detected (at time 12.1), the read clock frequency control circuit 19 determines that the data is written to the first frame memory V at time t2,
Frequency f of read clock signal RcK from t7. is gradually lowered from frequency f to frequency f5, and is temporarily maintained at frequency f3.

In FIG. 3, the times at which the frequency of the read clock signal RCK matches the frequency f are indicated by t5 and t8.

On the other hand, the frequency f of the read clock signal RCK.

During the period in which the frequency is decreased from the frequency f to the frequency f3 and the period in which the frequency is maintained at the frequency f3, the write frame memory is the first frame memory MF, and after that, the read frame memory is the first frame memory. Memory E
, the output frequency (t
v/N), and the read/write relative address detection circuit 20 determines whether the counted value has reached a value corresponding to two frames. This determination results in a count value of 2.
When the value corresponds to the frame (time 14.1.)
The frequency of the read clock signal RcK is gradually returned to the frequency f from the frequency f. In this state, the frequency f of the read clock signal RcIc. is the frequency f.

From 9 o'clock (time 15m 1..), the frequency f
.

is maintained until the next dummy flag pit is detected.

Note that the frequency f of the read clock signal RcK is here.

The purpose of gradually decreasing eB and increasing it to 7t is to avoid sudden frequency changes, and to reduce P in satellite broadcasting.
In the case of a CM audio signal or the like, this is a method to reduce deterioration in sound quality, especially deterioration due to sampling frequency fluctuation, when demodulating to an analog audio signal. Therefore, it is desirable that the read clock signal frequency control be performed for as long as possible within the dummy data transmission period, with minute frequency changes. For this purpose, the lower limit frequency f3 of the read clock signal RcK may be reduced.

In FIG. 3, the frequency f2 remains the original transmission lock signal frequency before time division multiplexing on the transmitting side.

When operating as described above, the transmission system or
A data error occurs in the demodulation system, and the dummy flag pit detection circuit 13 outputs a dummy flag detection output DMF. When the read clock frequency control circuit 19 receiving this dummy flag detection output DMF is controlling the read clock frequency, the clock frequency control state signal 5TA
TE is output to the dummy flag detection circuit 13, and the generation of the inhibition instruction signal WH and the dummy flag detection output DMF from the dummy flag detection circuit 13 is prohibited. Therefore, no further dummy flag bit detection output is generated during read clock frequency control, and the occurrence of long burst errors is suppressed.

On the other hand, the read/write address counter relative difference detection circuit 22 detects the relative difference between the write address signal WA and the read address signal RA. When the difference reaches a certain level, the write address counter 16 and the CFR extraction address counter 21 are initialized by the address difference detection signal ADint from the read/write address counter relative difference detection circuit 22. As a result, the occurrence of long burst errors can be avoided.

To be sure, if the dummy flag bit is missing and the read clock frequency cannot be controlled, a dummy signal will be written to the frame memory 17-1. If read clock frequency control is not possible, dummy data will be output as read data from the frame memory 17-1, and shock noise will occur when demodulating. In this case, by providing a PN signal (generator polynomial G←)=x + x +1) as dummy data, it is possible to avoid shock noise by ensuring that even if the dummy data is demodulated, it will be at zero level.

(Effects of the Invention) As explained above, according to the present invention, even when the dummy flag bits are inverted in the transmission system and the demodulation system and pseudo dummy flag bits are generated, During read clock frequency control, even if a dummy flag bit is detected, read clock frequency control based on the detection of the dummy flag bit is prohibited, so stable read a clock frequency control can be performed and burst errors can occur. is suppressed.

In order to ensure that the relative difference between the write address and read address of the storage device is detected and the write and read addresses are initialized before the two addresses overlap, the pseudo dummy flag bit is used to set the read clock. There is no possibility that the frequency control malfunctions and the write address and read address of the storage device overlap. This method suppresses the occurrence of burst errors.

In addition, as mentioned above, during read clock frequency control,
Furthermore, it may be possible to have both of prohibiting read clock frequency control and detecting the relative difference between the write address and read address of the storage device and initializing them before they overlap, but either one of them will have a sufficient effect. is obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a schematic diagram showing an example of a frame configuration after time division multiplexing. FIG. 3 is a diagram showing frequency changes of a read clock signal in an embodiment of the present invention. DESCRIPTION OF SYMBOLS 11... Frame synchronization signal detection circuit, 12... Write clock signal regeneration circuit, 13... Dummy flag bit detection circuit, 14... Channel selection instruction switch, 15... System timing generation circuit, 16.・・・
Write address counter, 17-1... Frame buffer memory, 17-2 and 17-4... Frame memory changeover switch, 17-3... Input selection switch, 18... Frequency dividing circuit, 19... - Read clock frequency control circuit, 20... Read/write relative address detection circuit, 21... Read address counter, 22
...Address counter relative difference detection circuit.

Claims (1)

[Claims] N-channel information signals having mutually different sampling frequencies or clock signal frequencies are set to the highest frequency among the sampling frequencies or clock signal frequencies,
Alternatively, time-division multiplexing is performed using a reference clock signal obtained by multiplying the frequency higher than the highest frequency by N, and a dummy signal is detected by receiving a time-division multiplexed signal in which a dummy signal is inserted into the portion where the information signal is insufficient. In the time-division multiplexing signal separation method, which temporarily reduces the read clock signal frequency without writing the information to the storage device, the information signal is read from the storage device and the original signal is restored. , stop the detection of the dummy signal, or detect the relative difference between the write address and read address of the storage device and initialize the write address and read address before the two addresses overlap, or at least either one of these is performed. A time division multiplexing signal separation method characterized by: