JPS62139588A - Sampling electronic musical apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field of 1] This invention relates to a sampling electronic musical instrument in which sampled a is rTH, and particularly relates to a technique for determining a loop area for repeated reading from sample storage means.

[Background of the invention] In conventional sampling electronic musical instruments that have a loop readout function, the setting of the loop area (address area that is repeatedly read out on the sample sound memory) is done based on the user's judgment. Specifically, the waveform data string of the sample sound stored in the sampling area is displayed on a display, etc., and the user can judge where to set the loop end address and where to set the loop return address to properly connect the loop. The loop area is determined by letting the machine know the address (point) specified by the user through key operations, etc.

Setting this type of loop area is labor-intensive and requires complicated operations, so it is desirable to have a machine that can automatically set the loop area.

However, there are problems with the introduction of automated loop configuration functionality.

That is, make sure that the no-ft area included in the sampling area (!) does not come before or after the loop joint, and also at the loop joint.

There are IF1 problems such as the need to prevent noise called click f7 from occurring, and these problems are currently considered to be extremely difficult to solve using automatic methods.

[Objective of the invention] This invention was made in view of the above-mentioned 111 circumstances. Our objective is to provide a sampling electronic f-instrument that takes into account the sound quality.

[9, Key Points of Akira] In order to achieve the above-mentioned objective, the present invention includes a first zero-crossing point and a first zero-crossing point for determining the first zero-crossing point within the sampling area of the sampling storage means and its phase.
a phase determining means; a second zero-crossing point determining stage for determining a second zero-crossing point that is within the sampling area and has data in phase with the phase of data at the first zero-crossing point; The key point is to have a loop determining stage consisting of a loop connection position 1 determination means for setting a zero crossing point of 2 as a joint of the loop.

[Operation of the Invention] FIG. 1 shows a schematic diagram of the present invention. During sampling, an external sound (sample sound) is recorded as a waveform data string in a preset sampling area of the sample storage means a. Since the sampling area is only as large or long as the external sound, it does not match the actual time length of the external sound.If the external sound is longer, sampling will occur before the external sound ends. The end of the area (end address) has been reached, and outside >'5 will not be recorded from the middle. 'LI! If the external sound is shorter, empty data with no sound will be stored near the edge of the sampling area.There should not be such a non-off area in the readout loop area.Furthermore, there should be no ff area like this in the readout loop area. If there is a significant change in the data, it becomes click noise. In order to eliminate these, the first zero cross point and phase discrimination means searches the sampling area, finds the zero cross point (first zero cross point), Roughly determine the phase of the waveform data at the zero crossing point. The term "phase" here refers to the nature of increase or decrease in the data string, and in this case, the in-phase second zero-crossing point determining means C searches the sampling area and detects the first zero-crossing point. Find a second zero crossing point that has the same phase as the phase of the data at . The above first zero cross point and second zero cross point are set as the point of loop connection II by the loop connection position setting stage d.For example, the first zero cross point is set as the loop return address in the loop read mode. Set the 2 zero cross point as the loop end address connected to the loop return address.

In loop read mode, when the waveform data is read up to the loop end address, it returns to the loop return address, and the address is sequentially incremented from there, and when it reaches the loop end address again, it returns to the loop return address again, and so on. The data in ' is read.

According to this IJ1, the data connecting the loops are both zero-crossing data, and their phases, that is, the properties of increase and decrease, are the same, so it is possible to significantly reduce the occurrence of no-RF conditions and click sounds when emitting sound. I can do it.

[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

The explanation includes the overall configuration, sound emitting function, CPU data read operation,
The CPU data loading operation, sampling operation, and loop setting operation are performed in this order.

The loop setting operation is an operation directly related to this invention.

One possibility to plan FIG. 2 is an overall configuration diagram of the embodiment. Needless to say.

The parts other than 2.3.4 are the sound source circuit, and each part is driven under the control of the CPU 2. This ff source circuit is broadly divided into a sound source memory 100 that stores lf as a wave and shape data string. Address generation circuit 101 that provides an address for accessing this sound source memory 100; Address generation circuit 1
B interval adjustment circuit 102 which adjusts the walking speed (and therefore the pitch) of the address step circuit that is troughed to 01. Sound source RAM (
a sample input circuit 103 for inputting sample data to the sample memory (sample memory); and an output circuit 104 for outputting the 7f color waveform data from the sound source memory loo as the final sound.
, a mode flag circuit for specifying the operating mode of the RF source circuit.

The rf source memory 100 here consists of a RAM II that stores a sample akg and a ROM 10 that stores one built-in tone (preset tone).

The address generation circuit 101 performs sampling of external sounds,
Enjoy the address increment circuit used when outputting internal sound data (sound emission), and its main elements are a start address check 5, an end address check 6, a return address latch 7, a 7F response counter 18. There is a matching circuit 19. Read/write 7 k'shi x5 ychi 27t*CPU 2
It is used for data transfer between 100 and 100. The address step circuit functions as a loop address generation circuit for RAM II when performing a performance using sample sounds.

The ff frequency adjustment circuit 102 includes a frequency setting latch 12°, a frequency counter 13. The increment circuit 14 consists of an output AND gate A1 and the like, and changes the address step speed of the address step circuit. Therefore, when playing on the f scale keyboard (so-called keyboard) in the key operation section 1, the step signal V) is supplied to the address step circuit at a speed that can reproduce the gf pitch (pitch) of the scale key. . Further, when sampling an external sound, a step signal is generated every so-called sampling synchronization, and the pitch adjustment circuit 102 functions as a sampling frequency generation circuit.

The sample input circuit 103 is connected to the microphone 34. Amplifier 35, A
/D converter 30 etc., A/D converter 30
converts and outputs the analog signal of the sample (() into digital waveform data at each sampling period, and inputs the conversion output to the sample RAM II. The output circuit 104 has an output data latch 16.D/
It basically consists of an A converter 17, an envelope applying circuit (consisting of an envelope latch 25, a D/A converter 26, and a multiplier circuit 22) for selectively applying an envelope to tone data, an amplifier 23, and a speaker 24.

The sound source circuit operates in the CPU as its basic operating mode.
2 is a read mode in which data is read from the sound source memory 100, a write mode in which data is read from the CPU 2 into the source memory 100, a manual mode in which sample sound waveform data is input from the sample input circuit 103 to the RAM 11, and waveform data in the sound source memory 100. There is a sound emitting mode in which a column is read out and sound is emitted through the output circuit 104. The read flag 28 and its peripheral circuitry are mode circuits used to specify the read mode, and the read flag 28 is set to ON (logic "1") in the read mode. The write flag 36 and its peripheral circuit are circuits used to specify the write mode, and the write flag 36 is set to on in the write mode.In the 0 manual mode, the on flag 15 is set.
and the A/D flag 21 is turned on. Further, in the sound emission mode, only the on flag 15 is turned on.

To simply describe the parts other than the sound source circuit, including their relationship with the sound source circuit, l is the key operation section, and in addition to the scale keyboard (!I board), there are various control keys, a T color selection key,
・It consists of a sampling key for starting sampling, a loop key, etc.). The CPU 2 uses a control section to detect whether a key of the key operation section 1 is turned on or off, and instructs the jY source circuit to perform a process corresponding to each key. 3 is an interface circuit, which controls the direction of data transmission between the CPU 2 and the sound source circuit, and an operation decoder 4 is connected to the CPU.
It decodes the commands from 2 and outputs latch clocks and gate control signals to be applied to various latches of the sound source circuit (start address switch 5, end address switch 6, return address switch 7, etc.). CPU2 has data to be set in various latches on the data bus DB! −
By sending a command to the operation decoder 4 and outputting the corresponding tick clock, the selected data can be set in the selected latch. Zarani C
The PU2 can send a command to the operation decoder 4 to output a memory read signal RMEM, control the G8, and read the data in the read data latch 8. At this time, the interface circuit 3 switches the data direction from the sound source circuit to the CPU. Gl-
GIO is a bus opening/closing switch composed of a 3-state buffer, and when the control human power C is "1", it is on and outputs the input as it is, and when it is "0", it is off and the output is in a high impedance state. Reference numeral 9 denotes a clock generation circuit, which generates two alternate pulses φI and φ2 (see FIG. 2).The clock signal t)CK output from the operation decoder 4 is all synchronized with the pulse φ2.

Emission 2 "[Nonji] We will mainly explain the sound emitting function, which is the basic function of the ET source plate circuit, and its operation.

The source circuit reads out the waveform data stored in the memory ROM10 or RAMII at intervals corresponding to the scale key and converts it into analog data.
(The number of actually sampled waveform data is much larger than this, but for convenience of drawing 8 data) is the relationship between the address of B and the corresponding data, and
This is the output analog waveform when the data of is read out every time t. Here, t is the time that determines the pitch; doubling t produces a sound that is one octave lower, and multiplying by 31/2 produces a sound that is one octave higher. Circuits that provide one t are the frequency setting latch 12) frequency counter 13, increment circuit 14, etc. On flag 15 is 9. This is a latch that is set to "θ" when "t" is not produced when sweating. On flag 15 as there is no sound now
Set output = 0.゛In this state, there is a key operation fit.
When the f-level key is pressed, the CPU 2 sets data corresponding to the pitch in the frequency a setting lar and chi 12.

On flag 15 output = 0 → R1 output = 1, so DG2 =
ON, Gl = OFF, and the frequency counter 13 is loaded with the data of the frequency setting latch 12. ). For example, now, frequency setting latch 1
If the data of 2 is 80 (H), frequency counter 13
The output is also ao (H), and the output of the rear gate A1 is 0. If the ON flag 15 is set to 1 here, R1 output is 0, G2=OFF, and Gl=ON.

In the increment circuit 14, the +1 input is always set to 1, so it is always incremented by +1. Therefore, 81 (H) is read into the frequency counter 13 at the next φl after the on flag 15 becomes 1, and is output at the next φ2.

After that, this process is repeated until FF (H) is output.
When FF (H) is output, A1 output = 1, Gl = OFF
, G2=ON, and 80()() is loaded from the frequency setting latch 12 to the frequency counter 13 again. By repeating these steps, the AI output will be 80 (H) to FF (
This is a timer that outputs "1" once during H). This interval corresponds to t in Figure 4C, and D in the same figure shows the movement of the form Theonfra'/l 5, which corresponds to C in the same figure.C in the same figure
is D on the output side of the analog waveform output data latch 16.
/ represents the output of the A converter 17, but the on flag 15
When is 0, inverter I2 output = 1 → reset l-1 of output data latch 16, and output data latch 16 output = all 0 (R shown in output data latch 16 etc. is a reset input, and when it is 1', reset -7)) -D/A controller 8-17 MSB power passes through I6, so at this time D/A
The converter 17 output will indicate the center voltage position. Also, in this circuit, the first address (start address) to read the waveform from memory (ROMIO or RAMI)
, a last address (end address) from which the subsequent addresses are not read, and a return address (return address) from which reading begins after reaching the last address, each with a start address.5. End addressler, Ciro.

The return address is set to 7. An example of these relationships when reading a certain waveform is shown in Figure 5.The address set in the start address latch 5 is incremented, and when it is read to the end address, it returns to the return address, and the address is incremented to the end address. read.

After this, repeat this until the ON flag 15 output = 0. When the ON flag 15 output = 0, ■2 output = 1, NOR gate NR1, NR2 output = O, so G4 = ON, G3,
G5=OFF, and during this time 7 consisting of two-phase F/F group
The data of the start address check 5 is loaded into the address counter 18. At this time, the data of the frequency setting latch 12 is loaded into the frequency counter 13 as described above. Matching circuit 19 is 1 for poems in which two sets of human power are in agreement.
Currently, the data of the 7-dress counter 18 (=the data of the start address check 5)=the data of the end address check 6, so its output is 0.

Here, when ON flag 15 output = 1, 1211 + force = O, G4 = OFF, coincidence circuit 19 output = 0 → 7 and gate A5 output; from 0, G5 = ON, inverter I4 output = 1, G3-0FF becomes address counter 18 The output passes through the increment circuit 2o and returns to the address counter 18. Immediately after the output of the on flag 15 becomes 1, the data of the frequency counter 13 has just started incrementing, and the data of the address counter 18 is incremented by A1 output = 0 → AND gate A2 output = 0 → +1 input of the increment circuit 20. Also, the H input of the output data latch 16 becomes the key operation part 1 at the same time as the ON flag 15 output = 1, but since the A2 output = 0, the AND gate Al output = 0 and the output data latch 16
No clock CK is output to the D/A converter 17, and the output of the D/A converter 17 remains at the center potential. Eventually, when the data of the frequency counter 13 becomes all l, Al output=1. A2 output = 1
The +1 input of the increment stage 1 path 20 becomes 1, and at the same time, G7 becomes ON, and the data of the address counter 1B is sent to the memory address AD through the address bus AB.

With A2 output = 1, inverter ■3 output = 0 → A3 output = 0, and when making a sweat sound, the output of A/D flag 21 is set to 0, so R2 output = 0 → memory output enable 0E. =0. Therefore, the data from the start address of the memory is output to RAM1l's output I10 or RO.
It is output from the output OUT of M10. However, RAMI
I outputs data when its chip selection input C5=O and 0E=0, and ROM10 outputs data when its chip selection input is equal to
0, data is output when d1=0. RAMII and R
Since the CS of OM10 is inverted through the inverter I8, it is assumed that they are not accessed simultaneously. Here, due to A2 output = 1, φ (synchronization pulse is 1
The output data latch 16 reads the data generated and output from the memory. This is converted into analog iti by the D/A converter 17, multiplied by an envelope by the 3l calculation circuit 22, and outputted from the amplifier 23 through the speaker 24. On the other hand, +1 passes through the increment circuit 20.
The address is read into the address counter 18 at φ1, and inputted to the memory's address AD through G7 at φ2, and when 0E=0, waveform data is output from the memory, and a pulse is sent to CK of the output data latch 16. By entering the data, the data is transferred to the CPU data latch 16.
is latched, and the D/A converter 17→multiplying circuit 22→
Sound is output through the speaker 24. Each time this series of operations is repeated, the data in the address counter 18 is incremented by 1, and the contents of the 7dress counter 1B = the contents of the end address check 6, and when the series of operations is repeated again, they match. Output of circuit 19=1. A2
Since output = 1, A5 output = l and NR2 output = 0 → G5 =
OFF, ■4 output = 0. NRI output = 1 (on flag 1
Since the output of 5 = 1) → G30N. Therefore, the data corresponding to the end address is output from the output data latch 16.
When the return address is latched to
The data in the memory is read into the address counter 1B, and the memory address is returned. After this, data from the return address to the end address will be repeatedly output until the on flag 15 is set to 0. Note that if the return address and end address are set to the same value, the hardware will stop the 7th address at the end address.Of course, the area from the middle address to the end address will be a silent area. (
10000000 data area), the output of the D/A converter 17 will be at the center potential after the middle address, so in effect, nothing will be output from the speaker 24 and the sound will be muted (zero multiplication). The circuit 22 is a multiplication circuit that expands or compresses the amplitude of the human power waveform (a) according to the human power potential (b), and when applying an envelope to the waveform read from the memory, the CPU 2 applies a value to the envelope latch 25 so that the output has the desired amplitude. CK (ENV)
Set via . The value of the input o-7' latch 25 is converted into an analog voltage by the D/A converter 26 and becomes the expansion rate or compression rate input to the multiplier circuit 22.

CPU Data Output - Next, the operation when the CPU reads data in the memory will be explained.

First, the case where the content of the on flag 15 = 0 and no sound is being produced will be described. Set the read flag 28=l and the write flag 36=A/D flag 21=0. On flag 15=0→I2 output=l→G20N loads the frequency counter 13 with the data of frequency setting latch 12, so Al output=0→A2 output=O I3 output=1
Since AND gate A4=1, a pulse synchronized with φ1 is output from the output of AND gate A6, and the human power is input to the data raft 8. At this time, since A2=0, G7=OFF, G60N (because of inverter X5), and the read/write address latch 27 is input to the memory address AD.

Also, due to write flag 36=0, AND gate A3=0
And since the A/D flag 21=0, when A8=0 and R2 output=0, 0E=0 and the data specified by the read/write address latch 27 is output. Therefore, write the address you want to read in the memory in the read/write address switch 27 in advance, write flag 36, A/D flag 21=O, read flag 28=
By setting it to 1, the data at the specified address in the memory can be read into the read data latch 8. After that, the CPU 2 sends the RM to the operation decoder 4.
By outputting EM=1 and turning on G8, the data in the read data launch 8 can be read through the bus DB. Also, l set in the address counter 18 is read into the 2FF 29 at φl, which is the same as the reading clock to the read data latch 8, and is reset by being output at the next φ2, and the read flag 28 becomes 0, so the read data latch 8 Prevents the reading clock from occurring more than once, and also sets the on flag 15 = 1 (during ffiff)
In this case, the above operation is called a cycle in which the output data latch 16 reads waveform data or a nine-input cycle (described later) of data from the A/D converter 30 (from φ2 to the next φ2 is called one cycle). It will be done in a cycle other than the In other words, AI output = 1 occurs during the waveform data reading cycle and the A/D converter 30.
This is only during the write cycle, and is 0 otherwise, so the above operation is performed by setting A2 to 0 in the cycle where AI output is 0.

Operation during CPU Data Next, the operation when the CPU 2 writes 41 pieces of data to the RAM II will be described. Read/write address latch 2
7 to 2! i Address you want to write, write data latch 3
Set the data you want to write to 1. After that, when the write flag 36 is set to 1, as in the case of the previous read, when the on flag tS=O, it is the cycle immediately after setting, and when the on flag l5=t, it is a cycle other than the waveform data read cycle or the A/D converter 30J write cycle. A3 output = 1. R2=1. At this time G
When 9=ON and OE becomes 1, the data in the write data latch 31 is input to Ilo of the RAM 11, and the Nant gate NAI generates a low active pulse synchronized with φ1. Input to I-include enable WE. Also, at this time, since G7=OFF and G6=ON, the data set in the write data latch 31 is written into the address set in the read/write address latch 27 three times. The CPU write cycle to this RAMII is only 1 cycle in the same way as the read by the 2FF32.

1ヱ! The operation in case of sampling will be explained below. First, the CPU 2 sets the following data in each tick.

A value corresponding to the sampling frequency is stored in the frequency setting latch 12, a start address of the sampling area is stored in the start address check 5, and an end address of the sampling area is placed in the end address check 6.

Read address check 7 has the same value as end address check 6, then on flag 15 = 1. A/D flag 21
=1. The frequency setting latch 12 starts counting from the on flag 15'=1, and the output of Al becomes 1 at every sampling period, and with that signal, the value set in the address counter 18 is outputted to the address bus AH while being passed through the increment circuit 20. Increment.

In the cycle that is output from the address counter 18 to the address bus AB, the A/D flag 21 = 1, so the A8 output = l → R2 = 1, the φ1 cycle pulse from NAI enters the WE, and the data of ■10 is transferred to the RAM 1l. It is stored in the specified address. A/D converter 30 is TRIGE
When a pulse enters R, the A/D during the previous TRIGER manual operation
The converted value is output to OUT and a new A/D conversion is started. Note that 2FF33 is the TR of the A/D converter 30.
RAM11 clean pulse without beard by IGER human power
of,! This is to ensure that there is no contradiction in the cycle. By the way, the first two pieces of data that enter the RAM II of the A/D converter 30 are not the data of the current sampled sound, and the CPU 2 sets the sampling address to a value that is two more than the start address specified in (a) above. Then, in order to detect the start of the real data of the sampled sound, the address is fixed to (start address + 2).7Ei Te, A / D core /< -p 3
The data written into RAMII HENO2 from o is transferred to CPUZ.
Check whether zero crossings occur in the data.

Strictly speaking, the CPU 2 turns the on flag 15 off after the write cycle of the A/D converter 30 is completed and before the next output cycle.

The data is read from the memory (RAMI 1 in this case) as described above, and it is determined whether or not the read data has reached a certain level (for example, a level corresponding to the LSB of the A/D converter 30). If not, in order to prevent the address from being updated, the address of the zero-crossing detection position (this is a value that is two times larger than the start address of the sampling area, and is set in the latch 27 by the CPU 2 in order to read the data for checking the occurrence of zero-crossing). address) is set in the address counter 18 via the start address check 5, and then the on flag 15 is set.
is turned back on, and this series of operations continues until the CPU 2 detects the occurrence of a zero cross. When the occurrence of a zero cross is detected, no further data is taken into the CPU 2, and the address counter 18 continues to increment from the address (start address + 2). As a result, the microphone 34. The actual sampled sound input via the amplifier 35 is A/D converted at each sampling period by the A/D converter 30, and is sequentially loaded into RAMI 1. When the end of the sampling area is written, the matching circuit is activated. L9=1 and at the first sampling time (At output=1), A5 output=1 and A/
The D flag 21 is reset and sampling ends.

Next, IJJ will explain the loop setting operation that is directly related to this invention. After the above-mentioned sampling operation is completed, when the user presses the loop key of the key operation unit 1, the CPU 2 enters the flow shown in No. 8 V54 to execute the loop setting process. First, in step s1, the CPU 2 selects the starting address of the valid data detected during the previous sampling operation, that is, the first address If1-4/ryhrty+y&l-t.
/, +'j-+,, +s) (see CPU data reading operation above). In this embodiment, this loop start address is two times larger than the sampling start address (has 1 (see above)). (refer to the sampling operation), and in the subsequent step S2, it is checked whether the read data is positive or negative.This data is the start data of valid data.In other words, the oil data is at the non-a level (typically is the median value 1 at B in Figure 4
0000000), therefore, if this data is positive, it means that the phase of change in this data is "increase", and if this data is negative, it means that the phase of change in this data is "decrease". It means that. Therefore,
If positive, the increase/decrease flag F is set to increase (“1′) (step S3); if negative, the flag F is decreased (“
0'') (step S3'').

In the following step S4, the end address at the time of sampling is selected as the read address, and certain data is read at that address.In the following step S5, the CPU determines whether the read data is at a silent level, or to put it simply, whether there is data or not. However, if there is no data, the read address is decremented by 1 and the data at the next lower address is read (step S6), and the process returns to step S5 again. Therefore, as shown in FIG. 6, if there is a silent portion on the end address side of the sampling area, it is determined that there is no data during that time in step S5. If it is determined that there is data at the read address, the process advances to step S7 and the read address is incremented by 1.

In step S8, it is checked whether the data is a zero cross or not, and the loop of steps S7 and 58 is repeated until a zero cross is found. When a zero cross is found, the process advances to step S9 and the phase of the data at that zero cross point is set to the loop start address (first It is determined whether the phase is in phase with the data at the zero crossing point). To be more specific, both data are in the same phase because the increase/decrease flag F of the first zero cross point is 1'', that is, the phase of the data at the first zero cross point is increasing (to be precise, as the address increases, data is increasing),
And, if the phase of the data at the second zero cross point is increasing (more precisely, if the data changes in the negative direction as the address decreases), or if the phase of the data at the first zero cross point is decreasing, and the phase of the data at the first zero cross point is decreasing, This is a case where the phase of data at two zero crossing points decreases. If they are not in phase, the operations from step S7 are repeated.

Without this in-phase check routine, as shown in A in Figure 7, in the case of loop readout, the phase will be reversed at the loop joint (loop connection position), causing a so-called click sound. If they are in phase, they will connect smoothly as illustrated in B in FIG.

When the in-phase is detected in step S9, the address value of the second zero-crossing point is set as the loop end address in step SIO, and the same value as the start address (first zero-crossing point) during the loop is set as the loop return address in step SIO. Set.

As a result of the above processing, the start address switch 5 in FIG.
The value of the start address at the time of a loop is set in , the same I1 is set in the return address check 7, and the value of the loop return address is set in the clock generation circuit 9.

[Modification] Note that in the flow shown in FIG. 8 above, the start of valid data (viewed from the end address) is searched by the routines of steps S5 and 86, but this is not necessary (in this case, step S4 After processing, go directly to step S8)
In the simplest method, zero-crossing can be detected by checking whether the signs of data at two adjacent addresses are reversed. In addition, in the simplest method, the phase of zero-cross data can be determined by the direction of sign reversal (from positive to negative, or from negative to positive) of data at two adjacent addresses; More accurate methods may be employed, such as analyzing the address data string.

Furthermore, in the embodiment, there are two types of phases (one is an increase and the other is a decrease), but the phases may be further divided into two types. The in-phase condition may be set to match within 30 degrees).

Furthermore, it is also possible to set the in-phase condition to be the case where the change patterns of increase/decrease of a series of data near the zero crossing match within a certain range.If the in-phase condition is made stricter, click Not only does the sound no longer occur, but the timbre that is felt audibly at the connection of the loops becomes unnatural.
The sense of discontinuity can be eliminated.

Furthermore, in the first embodiment, during sampling, the zero cross, which is the start of the actual sampled sound, is detected with the address fixed. This method results in
Minimize the length of the sampling area (memory capacity).

However, the present invention is not limited to this method, and the zero-crossing point that becomes the loop return address and its phase may be determined during the loop setting process after the completion of sampling.

In addition, although the loop key was used as a key to specify the loop setting process in the embodiment described in -H, it is not an essential element.
In general, loop processing as illustrated in FIG. 8 can be performed. In this case, the end of sampling becomes a condition for starting loop processing. The end of this sampling is
It can be detected by a software timer in CPUZ. Alternatively, the end of sampling may be notified to the CPU 2 from the sound source circuit side (for example,
A/D flag 2 reset upon completion of sampling
1 or by checking its status on the CPU 2 side). In this case, if desired, a key may be provided in the key operation sl that inhibits the loop function (when the key is turned on, Repeated reading can be prohibited by setting the return address check 7 to the same value as the end address check 6).

Further, in the loop processing of the embodiment described in I-, the start address and return address at the time of the loop are the same. This is particularly suitable when using real voices such as natural sounds or spoken words as external sounds (sample sounds).

However, the present invention is not limited to this, and loop playback may be performed using different points as a start address and a return address, respectively, as illustrated in FIG.

[Effect of Start L] As detailed above, according to the present invention, the first zero cross point and its phase are determined, and the second zero cross point that is in phase with this phase is determined.
Since it uses an automatic loop setting f-stage that searches for the zero cross point and sets one point as the loop connection point, the user does not need specially trained hearing ability or the ability to analyze waveform data using a display, etc. without doing,
Furthermore, the smooth loop connection virtually eliminates the occurrence of click sounds.

[Brief explanation of drawings]

Fig. 1 is a conceptual diagram of the present invention, Fig. 2 is a configuration diagram showing an embodiment of the invention, and Figs. 3, 4, and 5 are diagrams used to explain the sound source circuit shown in Fig. 1. , FIG. 6 is a diagram showing the relationship between the sampling area and the loop area in the embodiment together with the analog waveform of the sample sound, and FIG. 7 is a diagram showing an example of the address waveform during loop playback. B shows the in-phase loop connection according to this embodiment, and the eighth
The figure is a 70-chart of loop processing according to this embodiment. l...Key operation unit, 2...CPU, 5
...Start address latch, 6...
End address latch, 7... Return address latch, ll... RAM. Figure 1 E27CK Figure 3 Figure 5 Address Data Cφ Cape φφφφ Figure 4

Claims (6)

[Claims] (1) Loop determining means for determining a loop for repeatedly reading out a waveform data string from a sample storage means for storing external sound as a waveform data string in a preset sampling area; a first zero-crossing point/phase discrimination means for discriminating a zero-crossing point and its phase; a second zero-crossing point discriminating means for discriminating a second zero-crossing point that is within the sampling area and has the same phase as the first zero-crossing point; A sampling electronic musical instrument comprising loop connection position setting means for setting the first and second zero crossing points as loop connection positions. (2) In the sampling electronic musical instrument according to claim 1, the first zero-crossing point is a loop return address, and the second zero-crossing point is a loop end address with this loop return address as a return destination. A sampling electronic musical instrument characterized by: (3) In the sampling electronic musical instrument according to claim 2, the first zero-crossing point/phase determining means detects the occurrence of a zero-crossing of input data with a write address fixed at the time of sampling start. A sampling electronic musical instrument characterized by having a start zero cross occurrence detection means. (4) The sampling electronic musical instrument according to claim 2 or 3, wherein the first zero-crossing point is both a loop return address and a start address for reading sample sound. . (5) In the sampling electronic musical instrument according to claim 1, the loop determining means performs loop processing by the first zero-crossing point/phase determining means, the second zero-crossing point determining means, and the loop connection position setting means. A sampling electronic musical instrument characterized by having an instruction input means for instructing. (6) In the sampling electronic musical instrument having the memory described in claim 1, the first zero-crossing point/phase determining means sets the zero-crossing address closest to the writing start address of the sampling area as the first zero-crossing point, and 2. The zero-crossing determining means sets the zero-crossing point closest to the write end address of the sampling area among the zero-crossing points in phase with the first zero-crossing point as the second zero-crossing point, and the loop connection position setting means sets the second zero-crossing point as the second zero-crossing point. A sampling electronic musical instrument characterized in that an end address of a loop area is set, and a first zero crossing point is set as a return address to which this end address returns.