JPS62137934A - Delay compensation system - Google Patents

Abstract

PURPOSE:To obtain the delay compensation system for a digital communication system using >=2 standby lines switched synchronizingly with an active line by providing a delay adjusting means compensating a fixed delay difference between the standby lines to each standby line. CONSTITUTION:When a frame synchronizing circuit 51 detects that a code error rate of an active line SY S1 is deteriorated due to fading, a changeover command is outputted to a standby line SP1. A transmission changeover circuit of a transmission terminal station selects an output of a transmission code processing circuit and the output is sent in parallel through the active line SY S1 and the standby line SP1. The changeover command allows a synchronizing changeover circuit 71 to select and output the output of a delay adjusting circuit 6S1. As a result, the output of a delay adjusting circuit 61, that is, the signal sent through the active line SY S1 and the output of the circuit 6S1 (a signal sent through the standby line SP1) is inputted to the synchronizing switch. The delay time of the circuit 61 is adjusted so as to eliminate the fixed delay time difference between two inputs.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay compensation system, and more particularly to a delay compensation system for a digital wireless communication system that uses two or more protection lines that are switched synchronously with a working line.

[Conventional technology]

In digital wireless communication systems, code errors occur when there is a momentary interruption when switching lines. For this reason, in a digital wireless communication system that uses an N-to-1 system backup system in which there is one protection line for every N number of working lines, it is necessary to synchronize each working line and protection line in advance and perform synchronous switching. A line switching method (see Japanese Patent Application No. 143850/1983) is adopted to prevent instantaneous interruptions when switching lines. In order to synchronize two lines, it is necessary to equalize the propagation delays of both lines. The propagation delay difference includes a fixed delay difference due to the difference in electrical length between the two lines, and a variable delay difference due to delay fluctuations due to fading. For this reason, the receiving end of each working line is equipped with a delay adjustment circuit that compensates for the fixed delay difference between the working line and the protection line, and a delay adjustment circuit that automatically compensates for the variable delay difference of several bits and synchronously switches between the working line and the protection line. By providing a synchronous switching circuit, instantaneous interruptions during line switching are prevented.

Most conventional system backup systems have been N:1 systems, but as requirements for line reliability have become more sophisticated, N:2 system backup systems have also been proposed in recent years.

[Problem that the invention seeks to solve]

In a digital wireless communication system that uses two or more protection lines that are switched synchronously with the working line, a fixed delay is established between each of the working lines and each of the protection lines so that each working line can be switched synchronously with any of the protection lines. Although it is necessary to compensate for the difference, no delay compensation method has been proposed for this purpose.

An object of the present invention is to provide such a delay compensation system.

[Means for solving problems]

The delay compensation method of the present invention is a delay compensation method for a digital wireless communication system that uses two or more protection lines that are switched synchronously with a working line, in which a delay adjustment means for compensating for a fixed delay difference between the protection lines is connected to the protection line. Configured in preparation for the line.

〔Example〕

The present invention will be explained in detail below with reference to drawings showing embodiments. Figures 1 and 2 show a receiving terminal station 2 and a transmitting terminal station 1 constituting an embodiment of the delay compensation system of the present invention. FIG.

The transmitting terminal station 1 shown in FIG. The bipolar input signals 101 and 102 are divided into two and outputted by the hybrid 11.!2, which is controlled by a transmission switching control device (not shown), and input from the hybrids 11 and 12 and the coaxial switch 22. A pongee switch 2 which selects and outputs either one of the input from the test signal generator 93
1, 22, and a transmission code processing circuit 3S that converts the output of the coaxial switch 21 into a unipolar signal, converts the speed, inserts additional bits such as a frame synchronization signal and parity check bit, and further scrambles and outputs the two. A transmission code processing circuit 31 that processes the output of 11.12 in the same manner as in the transmission code processing circuit 3S, divides it into three parts, and outputs the divided outputs.
．． 32 and the outputs of the transmission code processing circuits 38, 31, and 32, and a transmission switching circuit which selects one of the three outputs under the control of the transmission switching control device and outputs it as modulated input signals Li5t and 11S2. 431, 482. Outputs of the transmission code processing circuits 31 and 32 that are not output to the transmission switching circuits 431 and 482, the modulated input signals 111 and 112, and the modulated input signals 11SI and 11S2 are input to respective transmitters (not shown). and wirelessly transmitted via the working lines 5YS1 and 5YS2 and the protection lines SPI and SP2.

The receiving terminal station 2 shown in FIG. 1 is a protection line SPI.

Demodulated signal 12S1.12S2゜1 which is the output of the receiver (not shown) of 5P2f or working line 5YSI, 5YS2
Frame synchronization circuits 5S1, 5S2, which detect deterioration of the bit error rate by inputting 21.122 and performing frame synchronization and parity check, and output the input as is.
51, 52, delay adjustment circuits 6S1, 6S2 whose delay time is adjustable and which delay the output of the frame synchronization circuits 5S1, 5S2 and output after three minutes, and frame synchronization circuits 51, 52 whose delay time is adjustable. The outputs of the delay adjustment circuits 61 and 62, which delay and output the output of A synchronous switching circuit 7S that outputs, a selection switch that selects and outputs either one of the outputs of the enhancement adjustment circuits 6S1 and 6S2 under the control of the reception switching control device, and a delay adjustment circuit that is controlled by the reception switching control device. Synchronous switching circuits 71 and 72 having a synchronous switch that synchronously switches the output of 61 and 62 and the output of the selection switch, and synchronous switching circuit 78゜71
．． A reception code processing circuit 8S, 81.82 descrambles the output of 72, removes additional bits, converts the speed, and further converts it into a bipolar signal and outputs it, and a reception code processing circuit 8S, which is controlled by a reception switching control device. 81 is selected and outputted as the output signal 131, and when the output of the reception code processing circuit 81 is selected, the output of the reception code processing circuit 8S is used to output the signal 150 which is output from the coaxial switch 92.
The coaxial switch 91 outputs to the coaxial switch 91, and the output of the received code processing circuit 82 and the signal 150 output from the coaxial switch 91 are selected under the control of the reception switching control device and output as the output signal 132. When the output of the received code processing circuit 82 is selected, the coaxial switch 92 outputs the signal 15° to the test signal detector 94, and the test signal detector 94 detects the signal 150. There is.

The operation of the embodiment shown in FIGS. 1 and 2 will be explained.

First, a case where both working lines 5YS1 and 5YS2 are normal will be described.

In this case, the test signal 140 is input to the transmission code processing circuit 3S via the coaxial switch 22゜21, converted into a signal, input to both the transmission switching circuits 481 and 482, selected, and output as modulated input signals 1181 and 11S2. Reserve line 48
1,482 in parallel. Reserve line 481,
The demodulated signals 1281 and 12S2 of 482 are input to the synchronization switching circuit 78 via frame synchronization circuits 5S1 and 5S2 and delay adjustment circuits 681 and 682. Delay adjustment circuits 6S1 and 6S are designed to eliminate the fixed delay difference between these two manual forces.
Adjust the delay time in step 2. The synchronous switching circuit 7S automatically compensates for the variable delay difference between the two human forces, and is controlled by the reception switching control device to synchronously switch and output the two human forces at a constant cycle.

This output is converted into a signal 150 by the received code processing circuit 8S. Therefore, the signal 150 is a test signal 140 transmitted over the protection line SPI and the test wave signal 140 transmitted through the protection line SP2, which are alternately switched. Test signal detector 94 detects signal 150
By detecting this, the communication quality of the protection lines SPI and SP2 is alternately improved.

On the other hand, input signals 101 and 102 are hybrid 11°1
2 to the transmission code processing circuit 31, 32 and converted into modulated input signals 111, 112 n current times, 1iisY
81.5YS2. Current line 5YSI.

The demodulated signals 121 and 122 of 5YS2 are input to the synchronization switching circuit 71.72 via the frame synchronization circuit 51.52 and the delay adjustment circuit &S61.62, and are selectively outputted and outputted by the reception code processing circuit 81.82 as the output signals 131, 132 km and is outputted to the receiving side multiplex carrier terminal equipment (not shown) via coaxial switchers 81 and 82.

Next, a case will be described in which the working line 5YS1 is switched to the protection line SPt by synchronous switching.

When the frame synchronization circuit 51 detects that the code error rate of the working line 5YS1 has deteriorated (due to aging, etc.), the reception switching control device detects this and switches the code error rate to the protection line SP.
Outputs a switching command to I. The switching command is sent to the reception switching control device, and the transmission switching circuit 481 is controlled by the transmission switching control device to selectively output the output of the transmission code processing circuit 31. As a result, the output of the transmission code processing circuit 31 is
It is transmitted in parallel by YS1 and protection line SP1. The switching command also controls the selection switch of the synchronous switching circuit 71 to selectively output the output of the delay adjustment circuit 6S1.

As a result, the synchronous switch of the synchronous switching circuit 71 receives the output of the delay adjustment circuit 61, that is, the signal transmitted by the working line 5Y81, and the output of the delay adjustment circuit 6S1, that is, the signal transmitted by the protection line SPI. The signal is input. The delay time of the delay adjustment circuit 61 is set to Am so that there is no fixed delay difference between these two manual inputs. Since the synchronization of the frame synchronization circuit 581 may be transiently disturbed due to the switching operation of the transmission switching circuit 481, the reception switching control device performs synchronization switching after confirming that the synchronization has been restored and the code error rate 9 has become normal. The synchronous switch of the circuit 71 is controlled to perform synchronous switching. During this changeover, the synchronous switch automatically compensates for varying delay differences between the two forces.

As a result of this switching, the input of the received code processing circuit 81 is switched from the signal transmitted by the working line SYS1, which has been input so far, to the signal transmitted by the protection line m5Pl, and the line switching is completed.

In this case, the test signal 140 is transmitted only through the protection line SP2. The reception switching control device controls the synchronization switching circuit 7S to selectively output only the output of the delay adjustment circuit 6S2. As a result, the signal 150 becomes only the test signal 140 transmitted by the protection line SP2, and the test signal detector 9
4 monitors the communication quality of the protection line SP2.

The delay time of the delay adjustment circuit 62 is also adjusted in the same way as the adjustment in the delay adjustment circuit 61.

The delay tone “festival circuits 6S1, 6S2, 61.6” explained above
Adjustment 2 eliminates the fixed delay difference between all lines, so in the same way as the working line H48YS1 is synchronously switched to the protection line SP1, the working line 5YSI is switched to the protection line SP2, or the working line 5YS2 is switched to the protection line SP2. Backup line S
It is possible to synchronously switch to P1 or protection line SP2.

For failures that cannot be overcome by line switching using the synchronous switching described above, such as failures in the transmitting code processing circuit or the receiving code processing circuit, line switching is performed by the same 1-lot switching device 21, 22, 91, and 92.

Due to such line switching, for example, the working line t%li! 5Y
When switching SI to protection line SPI, coaxial switch 21
outputs the output of the hybrid 11 to the transmission code processing circuit 3S, and the transmission switching circuit 4S1 selectively outputs the output of the transmission code processing circuit 3S. As a result, the signal transmitted by the working line 5YSl is also transmitted by the protection line SPI. The synchronization switching circuit 7S selectively outputs the output of the delay adjustment circuit 681, and the coaxial switching circuit 91 outputs the output of the received code processing circuit 8S as the output signal 131. The above operations complete line switching. In this case, the protection line SP2 can be used for synchronous switching with the working line 5YS2.

Incidentally, since the fixed delay difference between the protection lines SPI and SP2 can be compensated by using only one of the d-delay adjustment light circuits 6S1 and 6S2, either one of the delay adjustment circuits 6S1 and 682 may be omitted. However, if either one is omitted, it is necessary to change the frame synchronization circuit corresponding to the omitted delay and im adjustment circuit so that the input is divided into three parts and output.

The present invention has been described in detail above for the case where both the number of protection lines and the number of working lines are two.

It goes without saying that the present invention can be used even when the number of backup lines is three or more, and the present invention is not related to the number of working lines.

The delay compensation method of the present invention uses a delay adjustment circuit provided in the protection line to compensate for the fixed delay difference between each protection line. It is possible to compensate for the fixed delay difference between the third line and each of the protection lines. Therefore, if the number of backup lines is M (M is an integer of 2 or more) and the number of working lines is N (N is an integer of 1 or more), the minimum number of delay adjustment circuits required when used in the present invention is (M -1+N).

If the protection line is not provided with a delay adjustment circuit and the fixed delay difference between each protection line is not compensated for, M delay adjustment circuits are required for each working line to compensate for the fixed delay difference between each protection line. Requires circuit. In this case, the required total number MN of delay adjustment circuits is MN - (M-1+N) = (
M-1) Since (N-1)≧0, the number is greater than when using the present invention. CM-1+ to compensate for the fixed delay difference between each of the working lines and each of the protection lines.
It is obvious that N) or more delay adjustment circuits are required.

〔Effect of the invention〕

As explained in detail above, the present invention can be used to provide a fixed delay between each of the working lines and each of the protection lines in a digital wireless communication system that uses two or more protection lines that are switched synchronously with the working line. The effect is that a delay compensation method can be provided to compensate for the difference,
Further, the delay compensation system of the present invention has the effect of being economical because the total number of delay adjustment means required for a given number of working lines and a given number of protection lines is minimal.

[Brief explanation of drawings]

FIGS. 1 and 2 are block diagrams showing a receiving terminal station and a transmitting terminal station constituting an embodiment of the delay compensation system of the present invention. 61.62, 6S1, 6S2...Delay adjustment circuit, 71°72...Synchronization switching circuit. Agent: Susumu Uchihara, patent attorney (40,-

Claims (1)

[Scope of Claims] In a delay compensation method for a digital radio communication system that uses two or more protection lines that are switched synchronously with a working line, the protection line is provided with delay adjustment means for compensating for a fixed delay difference between the protection lines. A delay compensation method characterized by comprising: