JPS62133545A - Cache memory system - Google Patents

Abstract

PURPOSE:To improve the response speed of a cache memory by executing a control for loading only a part having a high possibility to be brought to an access, in the cache memory, at the time of a mishit. CONSTITUTION:In a memory 1, in case of a mishit, the block size dynamic variable mechanism 7 of a control part 6 executes a control so as to generate only the address of a part number (n) to 3 in an address generating part, based on a mishit address. This address is sent to an interface part 5, and a necessary part is read out of a memory device 12 and loaded to a load buffer 10. At the same time, a part requested by a processor 11 is delivered to the processor 11 through a data bus 13. In this case, a control part 6 transfers the address to an address tag. Also, the variable mechanism 7 decides a part in which an effective data in the buffer 10 is loaded, from mishit address information, stores the part in which the effective data is loaded, in a memory 8, and makes the corresponding valid flag effective.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Application of "Sanshu" The present invention relates to a cache memory system;
31 relates to a cache memory system in a storage hierarchy control system for computers.

lU(Long technology l ”V 'S-'7:/, :I-・Memory (Cach
CMemories: ^CM Com put, in
gSurveys, vol, I4. nol, 191+2
．． pp. 473-510>, in an information processing device equipped with a memory hierarchy, the main memory is divided into blocks of a certain size, and some of these programs can be accessed at high speed. By copying the data to the cache memory, if the data requested by the processor exists in the cache memory, the data can be copied to the cache memory.
Can be passed to Sosa quickly. This improves access speed from the processor's perspective. The size of this block (hereinafter referred to as block size) is generally taken as a power of two.

The cache memory records the block and copy located in main memory, and an address tag indicating the location of this block in main memory. The data memory is the part that records a copy of main memory, and the directory is the part that records address tags. A block corresponding to one address tag is the unit of mapping between main memory and cache memory.

When the gear source memory receives a data access request from the processor, it checks the directory to determine whether the requested data exists in the gear source memory. If the requested data is present in the gear source, the data is passed from the data memory of the cache to the processor. If the requested data does not exist in the cache (hereinafter referred to as miss filler 1), the main memory is accessed, the data is passed to the processor, and the block containing this data is copied to the cache.

There are full associative methods, set associative methods, and direct mapping methods for mapping between blocks in the main storage device and blocks in the cache memory. The fully associative method is a method in which an arbitrary block in the main memory can be mapped to a unique block f1 in the cache memory. direct·
In the mapping method, a cache memory block to be mapped is determined by the address where the main memory block exists. In the set associative method, cache memory blocks are divided into several groups, and cache memory blocks are divided into several groups, each having a glue 1 number determined by the address where the main memory block resides.
This method allows mapping to any block within the memory block.

The rate at which data requested by the processor exists in the cache and memory (hereinafter referred to as the hit rate) depends on the block size, and the hit rate improves as the block size increases. For this reason, the size of the block is
There is a cache memory which is larger than the portion that can be loaded by access (hereinafter referred to as bar 1-), and which requires multiple memory accesses to load one program. In this case, normally when a miss-hit occurs, the processor loads the requested data from the part that contains it, and at the same time passes this data to the processor so that it can load the remaining parts of the block and the processor's next part. The aim is to increase the overall processing speed by allowing multiple processes to be performed simultaneously. Therefore, if a miss occurs in the latter part of a block, this part is loaded from main memory, and then the gear is loaded to the block boundary, and then the remaining part, that is, the block First half bar 1~
17-code. This is called the "around road".

The sector buffer γ method is a method that can be applied to any gear source memory, including the full associative method, the cell-associative method, and the direct map method. It is the unit of mapping between main memory and gear source memory, and indicates whether a copy of main memory exists in data memory for each program in the sector.
Attaching the sodo flag to address tags in directories. In the sector method, Miss Hira 1-
The unit of loading from the main memory to the gear social memory when L is the block size. That is, the process
If a source requests data in main memory indicated by a certain address and causes a miss, it loads only the requested data or the program that exists into the cache, and then loads that program into the cache.・Tsuku's Paris... Nodo He So) ~ is effectively 4-ru.

[Problem to be Solved by the Invention 1] In the conventional cache memory system mentioned above, the access request related to the instruction code is usually moved from the lower address side to the higher address side of the main memory device. , Therefore, if the cause of miss high 1~ is instruction code fetch, the main memory of bar 1~ larger than the address that caused the miss hit will be stored as miss high 1~.
- is often accessed, and it is thought that there is little possibility of accessing a part of the main memory smaller than the address where the miss-hit occurred.

In cache memory where the buffer size is larger than the bus width, a miss occurs in the latter part of the block.
If ~ occurs, load this part first and then
After passing the data to Ce Sosa, bar 1- of the first half of the block
If the processor requests an instruction code in the next program immediately after an instruction code error (miss) due to a latch-around load, the cache There is a possibility that an around load is being performed between the computer and main memory. At this time, if the requested instruction code does not exist in the cache memory, the process...
The main storage device is not accessed by the access request...
This means that a response to the access request from the processor can be sent until the IP around load is completed. This has been one of the obstacles to improving the processing speed of a computer system using a cache memory whose block size is larger than the bus width. Furthermore, in this case, since the first half of the block, which is unlikely to be used, is loaded, there is a problem in that the main memory is accessed redundantly.

[Means for Solving the Problems 1] The cache/memory system of the present invention includes a data memory for recording a part of the main storage device, and a data memory for validating the data stored in the data memory.・An address tag to record whether the data is invalid or where it is in main memory, and if the data requested by the processor does not exist in the cache memory, that is, in the case of a miss. , a program address generator that enables the size of data transferred from the main memory device to the cache memory, that is, the program size, to be larger than the bus width, and the main memory device. In a cache memory having an interface section for accessing and a control section for controlling each of the above parts, the control section has a program size dynamic variable mechanism, and the address tag section has a dynamic program size variable mechanism. The unit is an integral multiple of the bus width.
Further, the present invention has a control mechanism that dynamically changes the size of the block transferred from the main storage device to the cache memory in the event of a miss. [Embodiment] The memory system has a determination unit that determines the type of data requested by the processor and controls the operation of the program size dynamically variable mechanism based on the determination result. Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a cache memory system according to a first embodiment of the present invention, and FIG. 2 shows mapping between a main storage device and a cache memory in this embodiment. In FIG. 1, the first embodiment of the present invention is a cache memory that dynamically changes the size of the program loaded from the main memory 12 to the cache memory 1 when a miss-hit occurs. In the memory system, the process :/?
, 1 ] is the address in address bus 14, control bus 1
When outputting information indicating an access request to 5 and requesting data in the part number n in the program,
The cache/memory control unit intersects the requested address with the address recorded in the address tag section 9 of Digits 1 to 3. Here, if there is a match, it is checked whether the Paris flag for Bart number n is enabled using the Hari Solo flag 8 for the sector indicated by the address tag. Bart, Paris about number n...I
If the write flag is enabled, it is determined that cache memory 1 has been loaded, and the requested data is passed from data memory 2 to processor ]1. , i.e. if there is no match for address tag 9, or for bar 1 to number n
If flag 8 is disabled, it is determined that there is a miss hit; in this case, the cache memory control unit 6
is the wait request line 1 from the processor 11 to the processor
6 is activated, the processor 11 is made to wait until the requested data is received from the main storage device 12. The operation of accessing the main memory 12 is shown below.7 When the processor 11 issues an access request, the address generation unit
2) Import the output address
When ~, the address generated by the address generating section 4 is sent to the main memory interface section 5, and in order to load the remaining parts from the fetched address, σ) At L and S are created, and the main memory interface section Send to 5. The main memory interface section 5 outputs these sent addresses to the address bus 18 and connects them to the control line 1.
The CPU 9 outputs an access request to the main memory 12, reads out the necessary data via the data bus 17, and sends it to the load bus 10.

The size of this load buffer 10 is equal to the block size.

Through this operation, the conventional cache memory control unit 6 loads the bart number 3 from bart number n to the buffer 10.
At the same time, the data requested by the processor 11 is passed to the 10 sensor 11 via the data bus 13 of the processor. Furthermore, after wrapping and loading parts from part numbers 0 to n-1 and sending them to the load buffer 10, the attos sent from the attos generator 4 is loaded from the address tag 9 and the load buffer 10. Store the program in data memory 2 and store the corresponding program in data memory 2.
Tsuku's valid flag was enabled.

In the cache memory according to the first embodiment, when a mistake occurs in part number n as before, the control section 6 of the cache memory performs the following operations. First, the block size dynamically variable machine 1147 existing in the control unit 6 causes the address generation unit 4 to generate only the Ats and Sus of part number n to 3 based on the addresses of misses 1 to 3. This address is sent to the interface section 5. The interface section 5 reads out the necessary part from the main memory 412 using this 'address, and sends it to the load bar 1.
Load to 0. At the same time, Florence Sosa 11
Aroce Sosa's Data Bus 1
3 through Process Sosa] When this operation is completed without passing to 1, the bar numbers 1 to 1 in the load bar sofa 10 will be changed to n.
The data is loaded from bar 1 to bar 3. At this time, in the control unit 6, the address recorded in the address generation unit 4 is transferred to the address tag 9.
Based on the information on the address, the part of the load bar sofa 10 where valid data is loaded is determined, and the part of the load bar sofa 10 where valid data is loaded, That is, the bar data of bar 11 numbers [) to 3 is recorded in the data memory 2, and in the pari sodo flag 8, the Hari Sodo flag corresponding to part numbers n to 3 is enabled.

FIG. 2 shows an example of a method of mapping in cache memory according to the present invention. In the 213th
Each sector 20 of the main storage device 12 is composed of a plurality of consecutive parts 22 to 26, and is divided into one or more programs 21.

That is, each block 21 is composed of N parts 23 to 26. The N parts constituting each block 21 are numbered from O to N-1. Each sector of the main memory 12 is mapped to this cache memory.
An address tag 9 is provided as a ping unit, and a Paris flag 8 is provided for each bart. Data memory 2 contains bar 1 to the boundary of pro 1,
That is, by loading the parts from bar 1-1 rl to N-1 into each portion 31 to 311, the corresponding node flag 8 is enabled. In other words, ノ<
- The data of the part whose part number is n to 3 corresponds to the part number from n to 3 in the data cut-out flag 8.

In other words, in the first embodiment, when the processor 11 requests data in the bar 23 with bar number 0, the parts 23, 24, 25, 26 with bar numbers 0 to 3 are requested.
A portion 31, 32, 33, which records these in the data memory 2 in the cache memory. Record it on j4,
Corresponding /< lid flag 27.28.29.3'O
Enable. In this case, the conventional sector method
It operates in the same way as flash memory. On the other hand, when Bromo Sosa 11 requests the data in bars 1-24 of bart number 1, the data in bars 1-24 of bart number 1 to 3 is
4.25.26 to 32°33.34 in data memory
and the corresponding Paris-nod flag 28.29.
Enable 30. Also, bromo lsu 11 or bar 1~
If you request the data at 25 to bar 1 of number 2, record -1 25.26 to the bar 1 number or 2 and 3/33.・Sodo flag 29.Enable 30 7Similarly, if the file system 11 requests the data in part 26 of No.ζ-1.number 3, then the Bart number is Bar 1 of
.about.26 is recorded at 34 in data memory, and the corresponding Paris node flag 30 is enabled. If 1 is added and the processor 11 requests data in parts numbered from -1 to 1 to 3, it does not access bars 1 to 3 in the first half of the block.

Next, the second embodiment of the present invention will be explained.7 Figure 3 shows the second embodiment of the present invention.6 In Figure 3, the second embodiment of the present invention will explain the type of data requested by the processor. By determining the size of the block that is loaded from the main memory to the cache memory, a cache system that dynamically changes the block size to be loaded from the main memory to the cache memory is developed.・Memory System, Cache, etc. A discriminating unit for discriminating the type of data requested by the bromo source 11 is provided in the control unit of the cache memory. Processor 11 is an address bus]4
The control bus 15 outputs information indicating an access request including information regarding the type of data requested to the address and control bus 15 to request the data in the parts numbered from bar 1 to number n within the block. The determination as to whether the data requested by the processor exists in the cache memory and the operation at the time of the request are performed in the same manner as in the cache memory shown in the first embodiment. The following describes the operation of accessing the main memory 12 in order to obtain the data requested by the file in the case of a mistake.

If a mistake occurs in the Bart number, the cache memory control unit 6 performs the following operations. First, the determining section 35 located in the control section 6 determines the type of data requested by the processor, and determines whether or not to dynamically change the program size. As a result, if it is determined that the block size will not be changed in accordance with Control is performed to send addresses from n to 3 and further addresses from part number O to n-1 to the main memory interface section 5.The main memory interface section 5 sends these sent attos to the address hash 18. The main storage device 12 is accessed by outputting an access request to the control line 19, and the necessary part is read out via the data bus 17 and sent to the load buffer 10. The bar 1 requested by the processor 11 is not passed through the processor's data bus 13 to the processor 11.
When the wrap-around loading of par 1~ from number 0 to r+-] is completed, the control unit 6 receives the address tag 9, which is sent from the address generation unit 71.
, records the block from the load buffer 10 into the data memory 2, and enables the valid flag of the corresponding block.

As a result of determining the type of data requested by the program in the determination unit 35, the program size is dynamically determined.
If it is determined that the flow size is to be changed, the flow size dynamic variable mechanism 7 is activated. In the control unit 6, the block size dynamic variable mechanism 7 controls the attos generation unit 11.
Control is performed so that only the attribution number 3 is generated from part number n. This address is Interfunis Department 5
As before, the interface unit 5 reads the necessary par 1 to 1 from the main memory 12 using this address and loads it into the load buffer 10. At the same time, the part requested by the processor 11 is passed to the processor 1 via the Bromo Tuna data bus 13. When this operation is completed, the part whose part number is 3 from n in the load buffer 10 is transferred to the processor 1 through the Bromo Tuna data bus 13. The data is now loaded. At this time, the control section 6 converts the address recorded in the address generation section 4 into an address.
Further, the program size dynamic variable mechanism 7 determines the part of the load buffer 10 where valid data is loaded from the information of the miss-hit address, and transfers it to the tag 9. The portion of the buffer 10 into which valid data has been rolled, that is, the data of par 1 to bar 1 with numbers n to 3, is recorded in the data memory 2, and the valid flag 8 is set to bar 1 with numbers n to 3. Enable the pari-nod flag corresponding to n to 3.

That is, in the second embodiment, it is determined whether or not to perform an around load depending on the type of data requested by the processor 1. By performing this control, the block size dynamic variable mechanism 7 is activated for data that is likely to be accessed in the direction of increasing addresses, such as instruction codes, and for data that is not uniform in the direction of access. A wrap-around rotor can be used for this purpose.

In this way, in the present invention, each par 1 in a sector has a helid flag, and in the event of a miss hit,
・Bar 11 number N-1 from part number n that woke up the throat
By controlling the loading into the par 14 cache memory, wrap-around loading of pars 1~ with bar numbers O to n-] into the gear source memory, which was conventionally done in the event of a miss hit. There is no need to do so. As a result, even if misses occur one after another, unlike conventional cache memory,
Access to the main memory no longer has to wait until the end of wrap-around loading, and redundant memory accesses can be reduced.

L? As is clear from the explanations in Sections J and H, the gist of the present invention is to finely divide the sector, which is the unit of mapping between main memory and gear memory, and to
・By preparing a flag, we take advantage of the fact that there is a high possibility that accesses to bromo/soza will go in the direction of higher addresses. Catch only? ,・To realize a control method for loading into memory. With this method, new misses and hits that occur while writing unnecessary data in the conventional cache and memory can be handled until the end of the software, around, and row. To avoid situations where access to a storage device is made to wait, and to reduce redundant memory accesses. It will be obvious that the present invention can be implemented in several ways without departing from the spirit thereof.

In the embodiment of the present invention, a cache memory system in which the size of the part is equal to the bus width is explained as an example, but it is also possible to set the part to be an integral multiple of the bus width and set the hard-nod flag to the part. The present invention can be applied to a system in which a miss occurs. ~ We have explained the method of loading a higher attos part into the gear sosh memory, but for accesses where there is a high possibility that the access will proceed in the direction of lower addresses, such as in the stack, it is necessary to load the part with a higher attos into the gear sosh memory. It is clear that a method of loading bars 1~ with a lower address into the cache memory can be realized more easily than the present invention. By controlling the loading of only the parts that are likely to be accessed at the time of access into the cache memory, it is possible to avoid problems in conventional cache memory. g. Avoid the situation where access to the main memory was made to wait until the end of the wrap-around load in response to a new error 1~ that occurred during the wrap-around load of important data, and This has the effect of reducing unnecessary memory accesses.

Furthermore, like the sector method, the present invention uses a sector, which is a collection of several parts, as a unit of mapping between the main storage device and the cache memory, and in the cache memory, a valid flag is prepared for each part within the sector. If a miss/hit occurs, the cache is removed from main memory.
A block is defined as the location to be loaded into memory, and among the parts in this block, only the part t~ whose address is higher than the part where the requested data exists, is loaded,
By enabling the corresponding valid flag, it is possible to avoid loading the first half of the block that is unlikely to be used into the cache memory, and improve the response speed of the memory. Figure 1 is a block diagram showing the configuration of the A. Yash memory according to the first embodiment of the present invention, and Figure 2 is a block diagram showing the structure of the main memory in the embodiment of the present invention. FIG. 3 is a diagram showing the configuration of a cache memory according to a second embodiment of the present invention.

DESCRIPTION OF SYMBOLS 1...Key position, -L, memory, 2...Data memory, 3...Tiref 1~S, 4...Address generation part, 5...Interface part, b...Control Department,
7... Pro-Tsuku size dynamic variable machine f; ■, 8...
・Valid flag, 9 ・Attis tag, 10 ・・
・Load buffer, 11...Brose Sosa,】2...
・Main storage device, 13.17...Data bus, 14.
18... Address bus, 15... Control bus, 16
...Way 1~Request line, 19...Control line, 20...
Sector, 21...Block, 22...26...Bar 1~. 27-30--Flag, 31-34--A portion for recording the part of the part number, 35--Discrimination section.

\、 0　　　　　　　〃〃 To To To To To ~ ~

Claims (1)

[Scope of Claims] 1. A data memory for recording a part of the main storage device, and a data memory for validating and storing data stored in the data memory.
An address tag is used to record whether the data is invalid or where in main memory it is located, and if the data requested by the processor does not exist in the cache memory, that is, in the case of a miss, the cache is removed from the main memory. A block address generator for making it possible to make the size of data transferred to the memory, that is, the block size, larger than the bus width; an interface unit for accessing the main memory; and each of the above. In a cache memory having a control section for controlling a portion, the control section is provided with a block size dynamic variable mechanism, and the address tag section is provided with valid bits in integer multiples of the bus width, A cache memory system characterized by having a control mechanism that dynamically changes the size of a block transferred from a main storage device to a cache memory in the event of a miss-hit.2. The block size is dynamically changed according to the type of data requested by the processor by having a discriminator in the control unit that discriminates the type and controls the operation of the block size dynamic variable mechanism based on the discrimination result. A cache memory system according to claim 1.