JPS62131296A - Electronic musical apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an electronic musical instrument that creates musical tones with a reverberation effect.

[Prior art]

Conventionally, when generating musical tones with reverberation effects, BBD (Bucket Br1cade
Device) element was used.

[Problems with conventional technology]

However, this BBDX child has a problem in that its unit price is high, leading to an increase in the cost of the electronic musical instrument.

[Purpose of the invention]

This invention was made in view of the above-mentioned circumstances, and its purpose is to provide an electronic musical instrument that can obtain a reverberation effect using a novel and inexpensive method that has not been seen before. .

[Key points of the invention]

In order to achieve the above-mentioned object, the present invention stores waveform data in advance in a storage means, reads out the waveform data stored in the storage means at a reading frequency corresponding to the pitch to create a musical tone, and creates a musical tone. The key point is to read out the waveform data at the same frequency as the readout frequency at a timing other than the timing at which the waveform data is read out a predetermined time after the start of sound emission, to create and emit another musical tone. be.

[Configuration of Example]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an overall circuit diagram of the waveform generator, and numeral 10 in the figure is a switch input section, and this switch input section 10 includes a sample 7" key for sampling and storing audio input from the outside. In addition to the scale key that adds a scale to this sample stored voice and stores it as a musical tone, and the echo key that adds a reverberation effect, various tones,
Keys are provided for specifying rhythm, chords, etc.

When processing samples using the sample keys above, microphone 3
The audio signal of the external audio input from 2 is amplified via the amplifier 18, timbre-controlled by the filter 19, converted to a digital signal by the A/D converter 520, and then converted to a digital signal by the A/D data set unit 21 at predetermined intervals. The sampled waveform data is stored in the waveform RAM II via the data select section 13.

When performing scale processing using the above scale key, the above waveform RAMI
The waveform data stored in I is read out step by step, passed through the data select section 13, and output to the CP by the multiplier JE unit 23.
Envelope set part 22a, 22 by UI
The envelope data set in b is multiplied via the envelope multi-brephizer circuit 33, and is emitted as a musical tone from the speaker 26 via the D/A converter 24 and amplifier 25.

In each of the above-mentioned processes, the data selection unit 13 selects the destination of each take in response to a data selection signal from the CPU 1.

Various address data necessary for accessing the waveform RAM II for each of these processes are stored by the CPU 1 in return address set sections 3A, 3B, start address set sections 4A, 4B, and end address set sections 5A, 5B.
are set respectively.

The start address set section 4AK is set with a write start (start) address or successive start (start) address of the waveform RAM II for the above sample processing or scale processing, and the end address set section 5A is set for the above sample processing or scale processing. The write final (end) address or continuation final (end) address of the waveform RAM II in the so-called "Zenga processing" is set. The return address set section 3AK sets the waveform R for the above-mentioned scale processing.
A read return address of the waveform RAMII when repeatedly reading waveform data from the AMII is set. The return address from the return address set section 3A or the start address from the start address set section 4A is sent to the RA via the address select section 6A.
After the M address set section 7AK is set, it is sequentially incremented by the increment section 8A and then sent to the RAM address set 117A again via the address select section 6A.
K is set to the waveform RAM via the multiplexer circuit 34.
I 1 is given. This sequentially incremented address is also given to the match circuit 9A, and when it matches the end address from the end address set section 5A, a match signal J+ is given to the CPUI, and the sampling input is completed or when the scale reading process is performed. The return address may be set or reset. In this case, each address is selected by the address select section 6A using an address select signal a from the CPUI.

The start address set section 4B is set with the successive start (start) address of the waveform RAMII for the above-mentioned scale processing, and the end address set section 5B is set with:
Similarly, the writing final (end) address or successive final (end) address of the waveform RAM II in the above-mentioned scale processing is set. The return address set section 3B is set with a read return address of the waveform RAM 11 when waveform data is repeatedly read out from the waveform RAM II in the above-mentioned scale processing. The return address from the return address set section 3B or the start address from the start address set section 4B is
After being set in the RAM address set part 7B via the address select part 6B, it is sequentially incremented by the increment part 8B, and set in the RAM address set part 7B again via the address select part 6B9, and then sent to the waveform RAMI 1 via the multiplexer circuit 34. Given.

This sequentially incremented address and matching circuit 9
When the end address matches the end address from the end address set section 5B, a match signal j2 is given to the CPUI, and the return address is set or reset during the scale successive processing. In this case, each address is selected by the address select section 6B in accordance with the address select signal a from the CPUI.

The increment period of the start address or return address mentioned above, and the sampling period during sample processing are as follows:
Time counter 4A, 14FB.

Reference value setting section 15A115B, timer matching circuit 16
A, 16B. Reference value setting section 15A
, 15B, a reference value corresponding to the above-mentioned increment period or sampling period is set by the CPUI and given to the timer matching circuits 16A, 16B, respectively, and each time the time count value from the time counter 14A 114B matches this reference value. , timer matching circuit 16A
.

16B outputs step signals C,,C,. The step signal CI is sent to the A/D converter 2 via the AND gate 31.
0 as a sample (number g), and in addition to being given as a latch signal i to the A/D data set section 21, an address increment signal is sent to the increment sections 8A and 8B via the multiplexer circuit 35 together with the sidewalk signal C1. and further RAM
Write/read timing signal g to control signal select section 27
given as. This RAM control signal selector 27
Based on the application of this write/read timing signal, a write/read signal R/W is outputted to the waveform RAM II. The selection of this write/read signal R/W is made by the CPU
This is done by the RAM control signal d from.

On the other hand, the step signals C, , C, from the timer matching circuits 16A, 16B are further applied as clear signals f, , f2 to the time counters 14A, 114B via OR gates 29 and 30, respectively.

The time counters 14A, 14B are also supplied with clear signals f, , f,
is given. In addition, the AND gate 31 includes a CPU
1 is opened by a sampling activation signal e from 1,
Sampling writing is possible only when this signal e is applied.

Further, when the echo key of the switch input section 10 is turned on, the delay time is set in the delay time setting section 36 by the CPU. After that, when you turn on the scale key, R
Reading of the waveform RAM II is started based on the output value of the AM address set section 7Aφ, and the delay counter 37 starts counting operation. The outputs of the delay time setting section 36 and the delay time counter 37 are given to a matching circuit 38, and when the delay count value of the delay time counter 37 matches this delay time, a matching signal k is outputted from the matching circuit 38, and the matching signal k is sent to the CPU 1. input. Then, reading from the waveform RAM 11 is started based on the output value of the RAM address set section 7B. This waveform RAM II is addressed by the multiplexer circuit 34 by alternately selecting output values from the RAM address set sections 7A and 7B.

[Operation of the embodiment]

Next, the operation of this embodiment will be described.

[Overall processing]

When the power switch (not shown) of the switch input section 10 is turned on, the CPU initializes each circuit shown in FIG. 1 (step Nl), and performs key sampling for the switch input section IO (step N, ), and if there is an on key, if that key is a sample key, then
If it is a scale key, the sample processing shown in Figure 3 is performed; if it is a scale key, the scale processing shown in Figure 4 is performed; if it is an echo key, the echo processing shown in Figure 5 is performed; if it is a key other than these, the corresponding processing is performed (step N, ~N,).

[Sample processing]

The above sample processing is performed based on the flowchart shown in FIG.

That is, the CPUI uses the start address set i4A
Set the start address in , and the end address in the end address set section 5A to designate the write area for external sound waveform data in waveform RAMI 1.Step S1
), the address select signal a1 for the start address set section 4A is given to the address select section 6 (step S!), and the start address is set in the RAM address set section 7A.

Next, the CPU sets a reference value that is half the sampling time of the external sound in the reference value setting section 15A to clear the time counter 14A (step Ss), and sets the waveform RA.
A data select signal for MIIK is applied to the data select section 13 (step S4), and a path line from the A/D data set section 21 to the waveform RAM II is opened.

Then, the CPU 1 supplies the sampling activation signal e to the AND gate 31 to open it, and supplies the step signal C1 from the timer coincidence circuit 16 to the A/D converter and the A/D data set section 21 (step S.). This step signal C1 is output every time the time count value of the time counter 14A matches the reference value corresponding to the sampling period of the reference value setting section 15A, so it becomes a sampling period signal and is outputted from the A/D converter 20, The A/D data set section 21 is driven at every sampling timing, and the increment section 8A is also incremented at every sampling timing, so that the start address is advanced toward the end address.

During this time, the external sound given to the microphone 32 is
8. The waveform data is sampled by the A/D converter 20 and A/D data set section 21 via the filter 19, and is written into the waveform RAM II via the data select section 13.

When the address incremented by the increment unit 8A matches the end address, the matching circuit 9A outputs the CP
A coincidence signal j is given to the UI.

Then, the CPU determines that the external sound waveform data up to the end address has been written and proceeds to step S.
a) Stop outputting the sampling activation signal e (step Sy) and end the sampling write process.

In this way, the external sound waveform data is stored in the molded RAM II.

[Echo processing]

The echo processing described above is performed based on chart 70 in FIG.

That is, the CPU determines whether flag E is on or not (step E+), and if it is not on, flag E)? Then, a delay time is set in the delay time section 36 (step Es). Further, if the flag E is on, the flag E is set to off (step E4) and no reverberation effect is imparted to the musical tone.

[Scale processing]

The above-mentioned scale processing is performed based on the cuff flow chart in FIG.

That is, the CPU determines whether the flag E is on or not (step Kl), and when the reverberation effect is not to be applied to the musical tone, that is, when it is determined that rNOJ, the return address set section 3A is executed.
Set the return address in , the start address in the start address set section 4A, and the end address in the end address set section 5A (step 2), give the RAM select signal d to the RAM control signal select section 27 (step Ks), and multiply. A data selection signal for the device 23 is given to the data selection section 13 (step 4),
A path line from waveform RAM II to multiplier 23 is opened.

Next, the CPU sets the reference value corresponding to the increment cycle according to the specified pitch of the second scale key to the reference value setting unit 15A.
to clear the time counter 14A (in step ). Then, every time the time count value of the time counter 14A matches the reference value corresponding to the increment period according to the specified pitch of the reference value setting section 15A, the step signal C5 is output, so that the increment section 8A
is incremented at the above-mentioned period, and the start address is advanced toward the end address. This step signal is given to the RAM control signal select section 27 and the read signal R
is also given to waveform RAM II. As a result, waveform data is read out from the waveform RAM II and provided to the multiplier 23 via the data select section 13.

At the same time, the CPUI sets envelope data in the envelope setting section 22a (6 to Kg in steps) at the timing when the step signal C1 from the timer-count circuit 16 is applied. As a result, the envelope data is multiplied by the waveform data given to the multiplier 23, and the signal is sent to the speaker 26 via the A/D converter 24 and the amplifier 25.
More musical sounds are emitted.

When the address incremented by the increment unit 8A matches the end address, the - number circuit 9A outputs CP
A coincidence signal j1 is given to the UI.

Then, the CPU determines that reading of the filter data up to the end address has been completed and goes to step 4.
), return address set unit 3 Gives the address select signal a for AK to the address select unit 6A to set the return address in the RA i'vl address set unit 7A instead of the start address (step KO), and thereafter returns. Repeatedly increments from address to end address.

Next, when applying a reverberation effect to a musical tone, when a scale key is pressed, the delay time counter 37 is first reset (step +, K+o). Then, set the return address in the return address set section 3A, the start address in the start address set section 4A, and the end address in the end address set section 5A (step 8.
), RAM select signal d? A data select signal for multiplication "a23" is given to the RAM control signal select section 27 (step KI2), and a data select signal for multiplication "a23" is given to the data select section 13 (step KI3).
Open the pass line to.

Next, the CPUI sets the reference value corresponding to the increment cycle according to the specified pitch of the scale key in the reference value setting unit 15A.
and clear the time counter 14. (step 8.). Right now, it's just after pressing the key, so match circuit 3
The coincidence signal from 8 is not input to the CPUI, and the step signal CI from the timer number circuits 16A and 16B is
C2 was not input either. Thereafter, each time the step signal C2 is output, waveform data is read out from the waveform RAM II as described above and is provided to the multiplier 23 via the data select section 13. Also, envelope data is set in the envelope set section 22a (steps K16 to
8. ). As a result, the waveform data given to the multiplier 23 is multiplied by the envelope data from the envelope set section 22a via the envelope multiplexer circuit 33, and a musical tone is emitted from the speaker 26 via the A/D converter 24 and amplifier 25. be done.

When the address incremented by the increment unit 8A matches the end address, the - number circuit 9A outputs CP
A coincidence signal j is given to the UI.

Then, the CPU 1 determines that reading of the dynamic data up to the end address has been completed and proceeds to step 8. ), the address select signal a1 to the return address set section 3AK is given to the address select section 6AK, and the return address is set in the RAM address set section 7A instead of the above-mentioned start address (step Kzo). Repeat the steps.

Then, the delay time set in the delay time setting section 36 is reached, and a coincidence signal k is sent from the - number circuit 38 to the CPU 1.
, the return address with the same value set in the return address set part 3A is set in the return address set part 3B, and the start address with the same value set in the start address set part 4A is set in the start address set part 4B. , end address set section 58
i'C Set the end address with the same value as that set in the end address setting section 5A (step 2).
1), the reference value setting section 15 is set in the reference value setting section 15B.
Set the same reference value as the reference value set in A, and clear the time counter 14B (step 2).After that, every time the step signal C2 from the timer number circuit 16B is output, the RAM address set section Waveform data is read out from the waveform ItAM 11 based on the address value set in 7B, and is applied to the multiplier 23 via the data selection section 13.
Envelope data is set in 2b (step 17, K2.). As a result, the waveform data given to the multiplier 23 is multiplied by the envelope data from the envelope set section 22b via the envelope multiplexer circuit 33, and a musical tone is emitted from the speaker 26 via the A/D converter 24 and amplifier 25. Ru. The envelope data set in the envelope set section 22b at this time is made smaller than the envelope data set in the envelope set section 22a.

Then, when the address to be incremented by the increment unit 8B matches the end address, the - number circuit 9B outputs the CP
A coincidence signal j2 is given to the UI.

Then, the CPU determines that the reading of the waveform data up to the end address has been completed (step 0), and gives the address select signal a for the return address set section 3B to the address select tS6B to set the return address to the above start address. Instead, it is set in the RAM address set m7B (step !5), and thereafter the walk from the return address to the end address is repeated. The sound emission state at this time is shown in FIG.

Through the above operations, a musical tone with a reverberation effect can be obtained.

Although the electronic musical instrument in the above embodiment is monophonic, it may of course be a 2t polyphonic instrument. Also, it doesn't matter how many polyphonic numbers you have. Although the delay time is fixed in the embodiment, it may be set arbitrarily. Further, although so-called two channels are used to obtain the reverberation effect, three or more channels may be used, and by doing so, a thicker reverberation effect can be obtained.

〔Effect of the invention〕

As explained in detail above, this invention stores waveform data in advance in a storage means, reads out the waveform data recorded in the storage means at a readout frequency corresponding to the pitch, and creates musical tones. , the above waveform data is read out at the same frequency as the above read frequency at a timing other than the timing at which the upper Hr2 waveform data is started after a predetermined time after the start of this musical tone, and another musical number is created. Therefore, musical tones with reverberation effects can be obtained in an inexpensive manner without using a BBD element.

[Brief explanation of drawings]

FIG. 1 is an overall circuit diagram of an electronic musical instrument, FIGS. 2 to 5 are flowcharts of overall processing, sample processing, echo processing, and scale processing, and FIG. 6 is a diagram showing a state in which musical tones are emitted. 1...CPU, 3A, 3B...Return address set section, 4A, 4B...Start address set section,
5A, 5B... End address set section, 10...
Switch input section, 11... Waveform RAM, 13... Data selection section, 20... A/D converter, 21...
A/D data set section, 32... microphone, 33...
Envelope multiplexer circuit, 34.35... multiplexer circuit.

Claims (1)

[Scope of Claims] A keyboard having a plurality of performance keys, a storage means for storing waveform data in advance, and a readout device for reading out the waveform data stored in the storage means at a readout frequency corresponding to the pitch of the pressed performance key. means for starting a counting operation after the reading means reads the waveform data from the storage means; and when the count of the counting means reaches a predetermined value, the waveform data is read from the storage means. another readout means that reads out the waveform data from the storage means at a frequency that is the same as the readout frequency at a timing other than the timing; and based on the waveform data read out by the readout means and the other readout means. An electronic musical instrument characterized by comprising a musical tone generating means for generating musical tones.