JPS62130073A - Deflection circuit - Google Patents
Deflection circuitInfo
- Publication number
- JPS62130073A JPS62130073A JP27044985A JP27044985A JPS62130073A JP S62130073 A JPS62130073 A JP S62130073A JP 27044985 A JP27044985 A JP 27044985A JP 27044985 A JP27044985 A JP 27044985A JP S62130073 A JPS62130073 A JP S62130073A
- Authority
- JP
- Japan
- Prior art keywords
- horizontal
- circuit
- output
- frequency
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Details Of Television Scanning (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、マルチスキャンモニタに好適な偏向回路に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a deflection circuit suitable for a multi-scan monitor.
信号源に応じて偏向周波数が変るマルチスキャンモニタ
には、水平発振周波数が15.75kHzのビデオ信号
から、31.5kHzの高密度キャプテン信号を含む広
範囲の信号源に対応できるよう、信号源の水平発振周波
数に自動追従する。g3図に示す偏向回路1が設けられ
ている。For multi-scan monitors whose deflection frequency changes depending on the signal source, the horizontal oscillation frequency of the signal source is Automatically follows the oscillation frequency. A deflection circuit 1 shown in Fig. g3 is provided.
この偏向回路1では、同期分離され或いは直接外部より
入力された水平同期信号が、μPB]377C等のIC
からなる水平発振回路2に供給される一方、周波数・4
正変換回路3に供給される。周波数・1正変換回路3は
、入力水平同期信号の周波数にほぼ反比例する1圧を発
生するが、この1圧は、電圧・′電流変換回路4を介し
て、水平発振回路2の発掘制御入力端子に供給される。In this deflection circuit 1, a horizontal synchronizing signal that has been synchronously separated or directly input from the outside is connected to an IC such as μPB]377C.
while the frequency 4 is supplied to the horizontal oscillation circuit 2 consisting of
It is supplied to the positive conversion circuit 3. The frequency/1 positive conversion circuit 3 generates a voltage that is approximately inversely proportional to the frequency of the input horizontal synchronizing signal, and this voltage is sent to the excavation control input of the horizontal oscillation circuit 2 via the voltage/current conversion circuit 4. Supplied to the terminal.
水平発振回路2は、入力水平同期信号によりトリガされ
て形成した鋸歯状波と、発掘制御入力端子に供給された
1流とを比較することにより、水平発振パルスを形成し
、この水平発掘パルスを後段の水平出力回路5に供給す
る。The horizontal oscillation circuit 2 forms a horizontal oscillation pulse by comparing the sawtooth wave formed by being triggered by the input horizontal synchronization signal with the first current supplied to the excavation control input terminal, and generates the horizontal excavation pulse. It is supplied to the horizontal output circuit 5 at the subsequent stage.
水平出力回路5は、水平発振回路2からの水平発振パル
スを一旦所定の1ぎ号レベルに増幅したのち、水平出力
トランジスタ(図示せず)のベースに印加し、水平出力
トランジスタのオン・オフ駆動とともに水平偏向コイル
(図示せず)に鋸歯状の偏向ME流を供給する。The horizontal output circuit 5 once amplifies the horizontal oscillation pulse from the horizontal oscillation circuit 2 to a predetermined signal level, and then applies it to the base of a horizontal output transistor (not shown) to drive the horizontal output transistor on and off. and a sawtooth deflection ME flow to a horizontal deflection coil (not shown).
上記従来の偏向回路1は1人力水平開!8信号の周波数
として1例えば15ないし34kHzの範囲でマルチス
キャンがOT能な構成をとっているが、入力水平同勘洛
号が高周波となるほど、発掘制御入力端子に供拾される
4流レベルが低下するため。The above conventional deflection circuit 1 can be opened horizontally by one person! For example, the configuration is such that multi-scanning is possible in the range of 15 to 34 kHz as the frequency of the 8 signals, but the higher the frequency of the input horizontal dokanraku signal, the higher the level of the 4 current signal provided to the excavation control input terminal becomes. To decrease.
水平発振回路2から出力される水平発振パルスのチュー
ティが、50%を越えて増大してしまう。The tute of the horizontal oscillation pulse output from the horizontal oscillation circuit 2 increases by more than 50%.
その清果、水平出力回路5内の水平出力トランジスタの
オフ時間が短くなる一方オン時間が長くなる丸め、蓄積
1荷効果等による影響で水平出力トランジスタのスイッ
チング動作が乱れる等の問題点があった。また、これと
は逆に入力水平同期信号が低lI!t1彼になればなる
ほど、水平発振パルスのデユーティが50%を下まわる
結果、′成力損失が増大し、最悪の場合、水平出力回路
5が動作停止してしまうことがある等の問題点があった
。As a result, there were problems such as rounding, where the off time of the horizontal output transistor in the horizontal output circuit 5 became shorter while the on time became longer, and the switching operation of the horizontal output transistor was disturbed due to effects such as the accumulated single load effect. . Also, on the contrary, the input horizontal synchronization signal is low lI! As t1 increases, the duty of the horizontal oscillation pulse falls below 50%, resulting in increased power loss and, in the worst case, the horizontal output circuit 5 may stop operating. there were.
この光力は、上記間狽点を解決したものであり、入力水
平同期信号の周波数に応じてデユーティが異なる水平見
損パルスを出力する水平発振回路と、この水平発掘回路
と水平出力回路の間lこ設けられ。This optical power solves the above-mentioned drawback, and is connected between a horizontal oscillator circuit that outputs horizontal miss pulses with different duties depending on the frequency of the input horizontal synchronization signal, and between this horizontal excavation circuit and the horizontal output circuit. l is provided.
前記水平同期信号の周波数に応じて、前記水平発振パル
スのパルス幅を変え、偏向出力条件と駆動条件を十分満
足する補正を行う補正手段とを設けてイ薄戊したことを
要旨とするものである。The gist of the present invention is to provide a correction means for changing the pulse width of the horizontal oscillation pulse in accordance with the frequency of the horizontal synchronizing signal and making corrections that sufficiently satisfy the deflection output conditions and drive conditions. be.
この発明は、入力水平同期信号の周a数に応じて変化す
る水平発掘回路の出力水平発振パルスのデユーティを、
前記水平同期信号の周波数に応じて前記水平見損パルス
のパルス幅を変えることにより、常にほぼ一定に保ち、
水平出力回路の駆動不足や偏向の乱れを防止する。In this invention, the duty of the output horizontal oscillation pulse of the horizontal excavation circuit, which changes according to the frequency a of the input horizontal synchronization signal, is
By changing the pulse width of the horizontal miss pulse according to the frequency of the horizontal synchronization signal, the pulse width is kept almost constant at all times,
Prevents insufficient driving of the horizontal output circuit and disturbances in deflection.
以F、この発明の夷4例について、第1.2図を参照し
て説明rる。第1.2図は、それぞれこの発明の偏向回
路の一実施例を示す回路構成図及び回路各部の信号波形
図である。Hereinafter, four examples of the present invention will be explained with reference to FIG. 1.2. FIG. 1.2 is a circuit configuration diagram and a signal waveform diagram of each part of the circuit, respectively, showing one embodiment of the deflection circuit of the present invention.
第1図中、偏向回路11は、水平発振回路2と水平出力
回路5の間に単安定マルチバイブレータ12を設けると
ともに、この単安定マルチバイブレータ12の保持時間
を可変制御するだめの制御回路13を、周波数・底圧f
aB路3に接続した回路構成をとる。In FIG. 1, the deflection circuit 11 includes a monostable multivibrator 12 between the horizontal oscillation circuit 2 and the horizontal output circuit 5, and a control circuit 13 for variable control of the holding time of the monostable multivibrator 12. , frequency/bottom pressure f
The circuit configuration is connected to the aB path 3.
単安定マルチバイブレータ12は、水平発振回路2の出
力である水平′i@振パルスがベースに印加されるトラ
ンジスタQ1が、エミッタ抵抗R+とR1の接続点を介
してクロック入力1子に接続されたIC14(IC名7
4LS123)を有しており。In the monostable multivibrator 12, a transistor Q1, to which the horizontal oscillation pulse output from the horizontal oscillation circuit 2 is applied to the base, is connected to the clock input 1 through the connection point between the emitter resistor R+ and R1. IC14 (IC name 7
4LS123).
このLC14fこ外を寸けされたコンデンサCの充1時
間lこ応した保持時間をもつ。コンデンサCの非接池1
JIII端子には、分圧抵抗R8,R,の妾続点と充電
1流oT変用のトランジスタQ、のコレクタが接続しで
ある。トランジスタQ、のエミッタは、抵抗R1を介し
て直流心源十Bに接続されており、ベースは、制御回路
13の出力1子に1妾続しである。This LC14f has a holding time corresponding to 1 hour when the capacitor C is charged. Unconnected battery 1 of capacitor C
The JIII terminal is connected to the connection point of the voltage dividing resistors R8, R, and the collector of the transistor Q for converting the first charging OT. The emitter of the transistor Q is connected to the DC core source B via the resistor R1, and the base is connected to one output of the control circuit 13.
制御回路13は、周波数・戒王R洟回路3の出力を反転
入力とする反転増幅器からなり、入力抵抗R6と帰還抵
抗R1の比に応じたゲインをもつ。The control circuit 13 is composed of an inverting amplifier that uses the output of the frequency converter circuit 3 as an inverting input, and has a gain corresponding to the ratio of the input resistance R6 and the feedback resistance R1.
非反転入力端子に接続した可変抵抗R8は、オフセット
調整のために設けられたものである。A variable resistor R8 connected to the non-inverting input terminal is provided for offset adjustment.
この+m例では、単安定マルチバイブレータ】2と制御
回路13が、水平発振パルスのデユーティを補正する補
正手段を構成する。In this +m example, the monostable multivibrator 2 and the control circuit 13 constitute a correction means for correcting the duty of the horizontal oscillation pulse.
ところで、入力水平同期1g・号の周波数が、あらかじ
め予想した周波数範囲のほぼ中間の周波数である場合、
水平ボ振回路2の出力水平発振パルス及び単安定マルチ
バイブレータ12の出力パルスは、ともにデユーティが
ほぼ50%であり、水平出力回路5内の水平出力トラン
ジスタのオン・時間とオフ時間は、はぼ等しい。By the way, if the frequency of the input horizontal synchronization signal 1g is approximately in the middle of the expected frequency range,
The output horizontal oscillation pulse of the horizontal oscillation circuit 2 and the output pulse of the monostable multivibrator 12 both have a duty of approximately 50%, and the on-time and off-time of the horizontal output transistor in the horizontal output circuit 5 are approximately 50%. equal.
ここで、入力水平同期信号の周波数が、あらかじめ予想
した周波数範囲内で低周波側に移動したとする。この場
合、周波数・α圧変良回路3の出力は、それまでよりも
減少し、当然制御回路13の負極性の出力は、絶対値を
増大させつつ減少する。このだめ、単安定マルチバイブ
レータ12内の充1框流可変用のトランジスタQ、のコ
レクタ1流が減少し、コンデンサCの充1時間が増大す
る。Here, it is assumed that the frequency of the input horizontal synchronizing signal moves to the lower frequency side within a previously predicted frequency range. In this case, the output of the frequency/α pressure changing circuit 3 decreases compared to before, and naturally the negative polarity output of the control circuit 13 decreases while increasing its absolute value. As a result, the collector current of the transistor Q for varying the charging current in the monostable multivibrator 12 decreases, and the charging time of the capacitor C increases.
その結果、第21囚ないしく′E5に示した如く、水平
発振回路2の出力のデユーティが50%をかなり割って
いるにもかかわらず、単安定マルチバイブレータ】2の
出力、すなわち補正された水平発振パルスのデユーティ
は、はぼ50%に保たれる。As a result, as shown in Section 21 or 'E5, even though the duty of the output of the horizontal oscillation circuit 2 is considerably less than 50%, the output of the monostable multivibrator 2, that is, the corrected horizontal The duty of the oscillation pulse is kept at approximately 50%.
従って、水平出力回路5内の水平出力トランジスタのオ
ン時間は、入力水平同期信号が低周波化した場合でも、
はぼオフ時間に等しく、これにより水平出力回路5の、
駆動不足或いは駆動停止といった事態を避けることがで
きる。Therefore, the on-time of the horizontal output transistor in the horizontal output circuit 5 is
is equal to the off-time, which causes the horizontal output circuit 5 to
Situations such as insufficient driving or stopping of driving can be avoided.
これに対し、入力水平同期信号の周波数が、あらかじめ
予想した周波数範囲内で高周波側に移動した場合は、周
波数・電圧変換回路3の出力は、それまでよりも増大し
、当然制御回路13の出力も負方向に増大する。このた
め、単安定マルチバイブレータj2内の充I乙α流可変
用のトランジスタQ8のコレクタ直流が増え、コンデン
サCの充電時間は短縮される。その債果、水平発振回路
2の出力のデユーティが50%をかなり越えているにも
かかわらず、単安定マルチバイブレータの出力デユーテ
ィは、はぼ50%以内に保たれる。従って、水平出力回
路5内の水平出力トランジスタのオン時間とオフ時間は
ほぼ等しく、従来のようにオン時間が大であるために蓄
積電荷効果すこより偏向が乱れる等の不都合を防止する
ことができる。On the other hand, if the frequency of the input horizontal synchronization signal moves to the high frequency side within the pre-predicted frequency range, the output of the frequency/voltage conversion circuit 3 will increase compared to before, and naturally the output of the control circuit 13 will increase. also increases in the negative direction. For this reason, the collector DC current of the transistor Q8 for varying the charge I and α currents in the monostable multivibrator j2 increases, and the charging time of the capacitor C is shortened. As a result, although the duty of the output of the horizontal oscillation circuit 2 considerably exceeds 50%, the output duty of the monostable multivibrator is kept within about 50%. Therefore, the on time and off time of the horizontal output transistor in the horizontal output circuit 5 are almost equal, and it is possible to prevent problems such as the deflection being disturbed due to the accumulated charge effect due to the large on time as in the conventional case. .
このように、上記偏向回路11は、入力水平同期信号の
周波数に応じて変化する水平発振回路2の出力水千発娠
パルスのデユーティを、単安定マルチバイブレータ12
と制御卸回路13からなる補正手段により、前記水平同
期信号の周波数に応じて水平発振パルスのパルス幅を変
えることにより、偏向出力条件と駆動条件を十分満足さ
せる構成としたから、低周波の水平同期信号が入力され
たときは、水平出力回路2内の水平出力トランジスタの
オン時間の減少を防止して、水平出力回路2の駆動不足
を解消し、高周波の水平同期信号が入力されたときは、
水平出力トランジスタのオン時間の増大を防止して、蓄
積電荷効果にもとづく偏向の乱れを解消することができ
る。In this way, the deflection circuit 11 changes the duty of the output water pulse of the horizontal oscillation circuit 2, which changes according to the frequency of the input horizontal synchronizing signal, to the monostable multivibrator 12.
By changing the pulse width of the horizontal oscillation pulse in accordance with the frequency of the horizontal synchronizing signal using the correction means consisting of the control wholesale circuit 13, the deflection output condition and the drive condition are sufficiently satisfied. When a synchronizing signal is input, the on-time of the horizontal output transistor in the horizontal output circuit 2 is prevented from decreasing, and insufficient driving of the horizontal output circuit 2 is eliminated. When a high-frequency horizontal synchronizing signal is input, ,
It is possible to prevent the on-time of the horizontal output transistor from increasing and eliminate disturbances in deflection due to the accumulated charge effect.
以上説明したように、この発明によれば、入力水平同期
信号の周波数に応じて変化する水平発振回路の出力水平
発振パルスのデユーティを、前記水平同期信号の周波数
に応じて前記水平発振パルスのパルス幅を変えることに
より、偏向出力条件と駆動条件を十分満足させる構成と
したから、低周波の水平同期信号が入力されたときは、
水平出力回路内の水平出力トランジスタのオン時間の減
少を防止して、水平出力回路の駆動不足を解消し、高周
波の水平同期信号が入力されたときは、水平出力トラン
ジスタのオン時間の増大を防止して、蓄積電荷効果にも
とづく偏向の乱れを解消することができる等の優れた効
果を奏する。As explained above, according to the present invention, the duty of the output horizontal oscillation pulse of the horizontal oscillation circuit, which changes according to the frequency of the input horizontal synchronization signal, is adjusted according to the frequency of the horizontal synchronization signal. By changing the width, the configuration satisfies the deflection output conditions and drive conditions, so when a low frequency horizontal synchronization signal is input,
Prevents the on-time of the horizontal output transistor in the horizontal output circuit from decreasing, eliminating insufficient drive of the horizontal output circuit, and prevents the on-time of the horizontal output transistor from increasing when a high-frequency horizontal synchronization signal is input. This provides excellent effects such as being able to eliminate deflection disturbances caused by accumulated charge effects.
第1.2図は、それぞれこの発明の偏向回路の一実施例
を示す回路構成図及び回路各部の信号波形図、第3図は
、従来の偏向回路の一例を示す回路構成図である。
2・・・水平発振回路、5・・・水平出力回路、11・
・・偏向回路、12・・・単安定マルチバイブレータ、
13・・・制御回路。1.2 is a circuit configuration diagram and a signal waveform diagram of each part of the circuit, respectively, showing an embodiment of the deflection circuit of the present invention, and FIG. 3 is a circuit configuration diagram showing an example of a conventional deflection circuit. 2...Horizontal oscillation circuit, 5...Horizontal output circuit, 11.
... Deflection circuit, 12... Monostable multivibrator,
13...Control circuit.
Claims (1)
水平発振パルスを出力する水平発振回路と、この水平発
振回路と水平出力回路の間に設けられ、前記水平同期信
号の周波数に応じて、前記水平発振パルスのパルス幅を
変え、偏向出力条件と駆動条件を十分満足する補正を行
う補正手段とを設けてなる偏向回路。A horizontal oscillation circuit that outputs horizontal oscillation pulses with different duties depending on the frequency of the input horizontal synchronization signal, and a horizontal oscillation circuit provided between the horizontal oscillation circuit and the horizontal output circuit, A deflection circuit provided with a correction means that changes the pulse width of a pulse and performs correction to sufficiently satisfy deflection output conditions and drive conditions.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27044985A JPS62130073A (en) | 1985-11-30 | 1985-11-30 | Deflection circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27044985A JPS62130073A (en) | 1985-11-30 | 1985-11-30 | Deflection circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62130073A true JPS62130073A (en) | 1987-06-12 |
Family
ID=17486439
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27044985A Pending JPS62130073A (en) | 1985-11-30 | 1985-11-30 | Deflection circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62130073A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6424571A (en) * | 1987-07-20 | 1989-01-26 | Nippon Denki Home Electronics | Horizontal output circuit |
-
1985
- 1985-11-30 JP JP27044985A patent/JPS62130073A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6424571A (en) * | 1987-07-20 | 1989-01-26 | Nippon Denki Home Electronics | Horizontal output circuit |
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