JPS62130015A - Pulse width modulation output device - Google Patents

Abstract

PURPOSE:To realize the titled device with small-size constitution by holding pulse width information and generating a pulse output signal in response to a detection signal from the 2nd storage means and an overflow signal from a free running counter. CONSTITUTION:When a coincidence signal line 211 of a CAM 201 is active at a point of time t4, an RS FF 501 is set and when the coincidence signal line 211 of the CAM 201 is inactive and an overflow signal line 401 of an FRC 400 is active the RS FF 501 is reset. For example, when a data O1H is set to the CAM 201, the RS FF 501 detects the active level of the signal line 401 of the FRC 400 and becomes a set state. Then the FF 501 is reset by detecting the active level of the coincidence signal line 211 of the CAM 201 at the next point of time. Through the operation above, the information data setting the length of a pulse output high level width by the controller to be connected is set to RAMs 101-104, then the width taking the high level of the pulse output is easily changed.

Description

[Detailed description of the invention]

FIELD OF THE INVENTION The present invention relates to a pulse width modulation output device. Conventional technology In recent years, microcomputers have become highly integrated due to advances in LSI technology, and peripheral hardware such as DMA, timer/counter, serial interface, board, and A/D converter has come to be mounted on a single chip. Ta. Among them, those equipped with pulse output devices are VTR,
It is indispensable for controlling motors, etc., both in the consumer field such as video disks and CDs, and in the OA field such as printers, plotters, and floppy disks. In particular, pulse output devices are very important in controlling external devices such as motors, and when controlling many external devices at the same time, it becomes necessary to provide multiple channels of pulse output. Generally, such a pulse output device includes a register (Pulse I! Iidt) for controlling the pulse width.
A pulse width modulation output device (hereinafter abbreviated as "PWM output device'") consisting of an hModulaLion register (hereinafter abbreviated as "PWM register") and a down counter is used. FIG. 5 shows a conventional PWM output device. In the figure, P
The WM output device 20 has a PWM unit 21 as its basic configuration, and has three units having the same configuration as the PWM section 21.
It has four types of independent PWM output functions. The four first PWM registers 701 to 704 included in this PWM output device 20 specify the high level period of the output pulse. Further, the other four second PWM registers 711 to 714 are for specifying the low level period of the output pulse. The four down counters 801 to 804 are
After presetting the values of registers 701 to 704 and 711 to 714, subtraction is counted according to clocks 811 to 814. The borrow lines 851 to 8511 of these four counters 801 to 804 correspond to the four T flip-flops 511.
~554. T flip-flop 551 that responds to Kurofuku 560 ~
PWM output terminals 601 to 604 are connected to the output terminal of 554. pWM registers 701-704 and 711-7111
is connected to other control devices (not shown) via a peripheral bus 900. The operation of one PWM section 21 of the PWM output device 20 configured in this way will be described below, but the other three PWM sections also operate in a similar manner. First, the down counter 801 alternately subtracts and counts the values set in the first PWM register 701 and the second PWM register 711 from another control device via the peripheral lotus. That is, when the down counter 801 subtracts the value of the i2PWM register 711 and an underflow occurs, the down counter 801 presets the value of the first PWM register 701, activates the borrow line 851, and sets the T flip-flop 551. . Next, the down counter 8 old subtracts the value of the first PWM register 701, and when an underflow occurs, the borrow line 851 becomes active and the T flip-flop 55
Reset 1. At the same time, the down counter 8 old presets the value of the second PWM register 711 and performs subtraction counting. Due to this operation, the down counter 801 reaches the first
Value of PWM register 701 and second PWM register 711
By alternately subtracting and counting the value of , the PWM output terminal 601 outputs a continuous pulse signal. The repetition period of this output pulse signal is the first
Old value of PWM register 7 and second PWM register 711
It is determined by the sum of the values of Further, the high level period 1 of the pulse signal is determined by the value of the I PWM register 701. When changing the ratio of the high level period to the period of the pulse signal output from the PWM section 21 (duty ratio), the first and second PWM registers 701 and 711 are sent from another control device via the peripheral lotus 900. Change the set value of. These changed registers 701
The duty ratio changes depending on the timing at which the values of 711 and 711 are preset in the down counter 801. Therefore, a pulse width modulated pulse signal is output from each of the four PWM output terminals 601 to 604. Problems to be Solved by the Invention However, such a conventional PWM output device requires one down counter and two PWM registers for one PWM output terminal. As a result, the device configuration becomes large, and especially when a large number of PWM output terminals are provided, the device configuration becomes extremely large and expensive. The present invention has been made in view of these points,
It is an object of the present invention to provide a pulse width control output device with a simple configuration. Means for Solving the Problems The pulse width control output device according to the present invention includes a free running counter that counts clocks, and a free running counter that stores pulse width modulation information. α means, a timing control section, a second storage means for holding the pulse width modulation information transferred from the first storage means and comparing it with counting state information of the free running counter, an overflow signal from the free running counter and and an output control section that generates a pulse output signal in response to the detection signal generated from the second storage means. In the pulse width control output device configured as described above, the free running counter counts a predetermined count clock, outputs information representing the counting state, and generates an overflow signal when an overflow occurs. Transfer of the pulse width modulation information from the first storage means to the second 1;α means is controlled by a timing control section. The counting state 11' from the free running counter and the pulse width modulation information are compared by the second and first means.

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If a person is bitten and a certain relationship is established in the image information, a detection signal is generated. According to the detection signal and the overflow signal, the output control section controls the pulse width and generates a pulse output signal. EXAMPLES Hereinafter, examples of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an embodiment of the present invention. Here, an 8-bit pulse width modulation output device is assumed. (1) Overall Structure In FIG. 1, a RAM 100 is connected to a peripheral bus 900 for receiving and receiving data on the pulse width of another control device (not shown). Furthermore, the RAM section 100
A PWM bus 270 is used to transfer the data to a content addressable memory (hereinafter referred to as "CAM") unit 200 that can detect a match between data being sent via the bus 900 and a count described below. A latch 410 that holds the count value of a free running counter (hereinafter referred to as FRC) 1100 that counts a predetermined count clock 402 is connected to a comparison data bus 280.
It is connected to the CAM section 200 via. Four CAMs 201 to 204 forming the CAM section 200
are connected to each of the four R-3-F Fs 501 to 504 of the R-S frill-luff flop (hereinafter referred to as R-3-F F) section 500 by four match signal lines 211 to 214. There is. The four timing control signal lines from the timing control section 450 are connected to the four RAMs 101 to 40 that form the RAM 100.
104 and four CAMs in the CAM section 200
It is commonly connected to each of 201-204. In addition, the overflow signal line 401 of the FRC400 is
It is commonly connected to the timing control section 450 and the four flip 70 tubes 501 to 504 of the R-S flip-flop section 500, respectively. The output terminals of the four R-3-FF501 to 504 are the four P
It is connected to WM output terminals 601-604. (1-2) Configuration Each component function The functions of each component shown in FIG. 1 will be explained. (i) RAM unit 110 The 0RA unit 100 is a memory for temporarily holding data to be written to the CAM 200, and has four RAMs.
It consists of 101 to 104. When the four timing signal lines 411 to 414 connected to these become active, the data held in the RAMs 101 to 104 are outputted via the PWM bus 270. (ii) CAM unit 200 The CAM unit 200 is for comparing two pieces of data, and consists of four CAMs 201 to 204. P
The data held in the RAM 100 supplied via the WM bus 270 and the data held in the latch 41 ( ) supplied via the comparison data bus 280 are compared, and when they match, four matches (3 retrace lines 211 to 2111 becomes active. Also, when the four timing signal lines 411 to 414 become active, the data on the PWM lotus 270 is transferred to CAM2.
01-2f) Import and hold in 4. (Mountain) FRC 400 The FRC 400 counts a predetermined count clock 402, and when it overflows, it activates the overflow signal line 401. (1v) Latch 410 The latch 410 holds the count value of the FRC 400 at a predetermined timing, and always outputs the held data to the comparison data bus 280. (V) Timing control unit 450° The timing control unit 450 controls the overflow signal line 40
1 becomes active, four timing signals 511
11 to L114, RΔM1 old to 1
The held value of 04 is sequentially transferred to the CAMs 201 to 2011. (vi) R-37 flip-flop unit 500R-S flip-flop unit has four reset priority type R-S-F
It consists of F501 to F504. Each R-3-FF is
Match signal lines 211-2 of four CA M2O1-204
If each of 14 is active at a predetermined timing, it is reset. In addition, the coincidence signal lines 211 to 214
are inactive at a predetermined timing, and are set if the overflow signal line 401 from the FRC 400 is active. A cell 210, where a data holding unit 220
, comparison section 230, write gate 260, match signal line 2
11. It has a data line 2711, a comparison line 2811, a write signal line 261, and a sample signal line 251.
Match signal line 211 has a precharge gate 240 and a precharge signal line 241. (a) Data line 271 and comparison line 281
The data line 271 is a positive logic data line (hereinafter referred to as "
It consists of a negative logic data line (hereinafter referred to as "Q line") 272 and a negative logic data line (hereinafter referred to as "Q line") 272. Similarly, the comparison line 281 is composed of a positive logic comparison line (hereinafter referred to as "CQ line") 282 and a negative logic comparison line (hereinafter referred to as "CQ line") 283. (b) Data Holding Unit 220 When the write signal line 261 becomes active, the data holding unit 220 opens the write gate 260 and takes in and holds the data on the Q line 272 and the data on the Q line 273. (C) Comparison section 230 The comparison section 230 includes four comparison gates 231 to 234 and a sample gate 250. To detect a match between the data holding section 220 and the comparison line 281, first, the match signal line 211 is precharged by making the precharge signal line 241 active and opening the precharge gate 240. Thereafter, sample gate 250 is opened. CQ line 282 and negative logic holding line 223 are both 1
'' or CQ line 283 and positive logic holding line 2
22 are both "1", that is, the comparison line 281
When the values of the data holding unit 220 and the data holding unit 220 do not match, the signal level of the match signal line 211 becomes “0”. Further, if the sample gate 250 is opened when the values of the comparison line 281 and the data holding section 220 match, the signal level of the match signal line 211 is held as "1". By performing the precharge operation and the sampling operation in this manner, it is possible to detect coincidence between the CAM cell 210 and the comparison data bus 280. If CΔM2O1 is formed by connecting eight such CAM cells 210 in parallel to the match signal line 211, if all eight CAM cells are precharged and sampled when they match the comparison data bus 280, the match signal line 211 becomes active. Furthermore, data line 27
1 and the comparison line 281, four CAMs having the same configuration are connected in parallel to form four CAMs 201 to 204. (2) Overall operation Next, the overall operation of the above-mentioned configuration will be explained. Here, P
The basic timing of the WM output device 10 is based on the timing of each level transition of the count clock 402. Repeated operations are performed during periods T1 to T, which are one crotter period. ll-1, Transfer from RAM section 100 to CAM section 200 The FRC 400 performs an increment operation based on the count clock 402 shown in FIG. (See (b)). Also,
The latch 410 latches the count value of FRC4QO in synchronization with time t2 (see FIG. 3(c)). FRC4
00 performs counting, and when it overflows, the overflow signal line 1I01 is activated (Fig. 3 (D)).
reference). This active state continues from time 1+ to time t1 of the next cycle, and from time t1 to t8 in the meantime, to time t6.
~th. In synchronization with this time point ta, the timing control section 450
The timing control signal line 411 is made active for a period T1 (see FIG. 3). By thus making the timing control signal line 411 active, the RAM 101 of the RAM section 100 transfers its held data to P
It is output to the WM bus 270 (see FIG. 3 (e)). Then, in synchronization with time tb, CAM2 of the CAM unit 200
01 takes in and holds the RAM10IO value on the PWM bus 270 (see FIG. 3(G)). Similarly, the timing control unit 450 sequentially activates the other timing control signal lines 412, 413, and 414 during periods T2, T3, and T, respectively (
(See Figure 3 (S), (W) and (Y)), RAM10
2. Set the holding values of 103 and 104 to PWM verse 270
(See Figure 3 (E)). Also, time td,
In synchronization with the timing of tr and th, the RAM 102
．． The holding value of 103 right and 104 is CAM202.203
and is written to and held in 204 (Figure 3 (N)).
, (wa) and (yu)). By such an operation, information on the high level width of the output pulse is set in the CAMs 201 to 204. (2)-2. Comparison of data Next, the operation of comparing data between the CAMs 201 to 204 and the latch 410 will be explained. The CAM 201 precharges the match signal line 211 in synchronization with time t2 (see FIG. 3 (h)). Subsequent time point t3
By performing sample operation in synchronization with CAM 2
When all the old CAM cells and all the bits of the latch 410 match, the match signal line 211 becomes BI. As a result, a match between the CAM 201 and the latch 410 is detected. In the same manner, precharge is performed at time t5, and time t5 is precharged.
By sampling the CAM 202, a coincidence is detected in the CAM 202 (see FIG. 3). Furthermore, coincidence detection is performed for all CAM cells at time t6, t, and coincidence detection for all CAM cells is performed at time t8, tl (see Figure 3 (see) and (shi)).
. ■-3. Pulse Width Varying Operation Next, the output pulse width varying operation will be explained. R-3-FF 501 is CA M at time t,
The match signal line 211 of CAM2O1 is set active, and the match signal line 211 of CAM2 old is set to active at time t4.
is inactive and the overflow signal line 401 of the FRC 400 is active. For example, when setting data CILH to all CAM cells,
At time t4, the overflow signal line 40 of FRC400
R-3-F2O3 detects the active level of 1 and enters the set state. Then, at the next time t4, CAM
201'f! If it detects the active level of line 21+, it enters the reset state (:rS31J(n)
reference). Through such an operation, the control device connected to another R
By simply setting AM101 to AM104, the width at which the pulse output takes a high level can be easily changed. In the embodiment described above, the timing control section 11.5
0 in the RAM 101 by the overflow signal 401.
The timing of transferring the held data of ~104 to CAM2O1~204 is controlled. In response, the timing control unit 450 activates the coincidence signal lines 211 to 214 of the CAMs 201 to 204, thereby causing the RAM1
Data transfer from CAMs 01 to 104 to CAMs 201 to 204 may be controlled. The timing in that case is shown in FIG. 4, and will be explained below with reference to FIGS. 1 and 4. The timing control unit 450 controls the coincidence signal line 2 of the CAM 201.
11 is active, the period T1
The timing signal line 111 is made active throughout (see FIGS. 4(f) and (g)). In this way, during the period when the timing signal line 1111 is active, the RAM 10I transfers its held data to the PWM bus 2.
70 (see FIG. 4(d)). CA M2O1
captures and holds the value held in RAMl0I on the PWM bus 270 in synchronization with time tb during the period when the timing signal line 411 is active (see FIG. 4(E)). Similarly, when the coincidence signal lines 212, 213 and 214 of the other CAM2O2, 203 and 204 become active, the timing control unit 450 controls the timing signal line 412.4 over the periods T2, T3 and T4, respectively.
13 and 414 are activated (Fig. 4 (N))
(see w) and (ri)). These timing signal lines 41
2. Period during which 413 and 414 are active RAM10
2.103 and 104 send their held values to the PWM bus 27
Output to 0. And CAM 202.203 and 204 connect timing signal lines 412.413 and 414
At times td, tf and th during the period when is active
In synchronization with , the values held in RAMs 102, 103 and 104 are fetched and held. Note that the operations other than the data transfer operation to the CAM section 200 are the same as those in the case described above. In this way, by configuring PWM with RAM5CΔM and FRC and utilizing the overflow of the FRC, the number of PWM output terminals can be increased simply by adding RAM and CAM. Since RAM and CAM have an array structure, they are extremely small hardware compared to a data counter. Furthermore, since the CAM has a bus dedicated for comparison in addition to the data bus, there is a high degree of freedom in the timing of data comparison. Therefore, multi-channel PWM hardware is easy to implement. Effects of the Invention According to the present invention as described in detail above, a multi-channel pulse width modulation output device can be realized without increasing the device configuration, and is extremely effective in practical use.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a pulse width modulation output device according to an embodiment of the present invention. FIG. 2 is a connection diagram showing the circuit configuration of a unit bit cell of the CAM shown in FIG. 1. Figures 3 (A) to (S) and Figures 4 (A) to (Evening) are
FIG. 6 is a timing chart for explaining the operation in each embodiment of the present invention. FIG. 5 is a configuration block diagram showing a conventional example. (Main reference number) 10.20...Pulse width modulation output setting, lOO...RA
M part, 200... CAM part, 210... CAM cell, 211-214... CAM coincidence signal line, 220...
・Data holding section, 230.. Comparison section, 270.. PWM bus, 280.. Comparison data bus, 400.. Free running counter (FRC), 1l
O1...Overflow signal line, 1111-1114...Timing signal line, 500
・・R-S flip-flop section, 701 to 704.71
1~714...PWM Regisc, 801~804
・・Down counter, 900・・Surrounding bus

Claims (1)

[Scope of Claims] A free-running counter that counts a predetermined count clock; a first storage unit that retains pulse width modulation information; a timing control unit; a second storage means that holds the transferred pulse width modulation information, receives counting state information of the free running counter, and generates a detection signal when a predetermined relationship is established between the two pieces of information; an output control unit that controls a pulse width and generates a pulse output signal based on an overflow signal of a free running counter and a detection signal generated by the second storage means; Width modulation output device.