JPS6212984A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To monitor an access time of an actual memory, to require no wasteful waiting time, and to attain a high speed data processing by outputting an internal operating state display signal from the device. CONSTITUTION:Since a DTAK signal is generated at a timing equal to an access time of an actual memory, a circuit for checking the access time in a memory device is disposed to output this signal. An internal operation state display signal outputted from the memory device has to output from an access operation start signal to an operation completion pulse, so that a set and reset type flip flop (RS flip flop) circuit is employed. If the operation start pulse is inputted to a setting terminal, and to the operation completion pulse setting terminal, respectively, the output of this flip flop is used as an internal operation state display signal and is outputted from the device.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to semiconductor memory devices used in various information processing devices, including ROM (read only memory), RA
M (Random Access Memory).

When using conventional semiconductor memory devices, memory access time (τACC) is a very important parameter. For example, in a computer system, the CPU (central information processing unit)
Assume that there are 1, 2 and 3 memories, etc., and the CPU requests data stored at address 100 of the memory. τACC is τ1
memory device, the CPU must wait 71 or more times before capturing the data that appears in the device's output bin. Conventionally, such processing has been performed using the following method.

(a) The CPU outputs a start signal and an address signal at the same time as starting memory access. Next, there is a signal that indicates whether the correct data has arrived at the data input pin of the CPU, a normal data transfer acknowledge (DT).
AK:DATATRANSFERACKNOWLEDG
E) Data is captured when a signal called signal is received.

If DTAK does not arrive, the CPU stops operating and enters a wait state.

(b) The system designer created this DTAK signal as follows. First, since the worst access time τma of each memory element to be used is known, τm
A circuit having a propagation delay time larger than that of A is prepared, and the access start signal output from the CPU is input to this circuit. Since the output of this circuit is delayed by τmaw or more from the start of access, it can be used as a DTAK signal.

FIG. 5 shows the operation of such a conventional system. In this figure, 5TRT is the operation start signal.

DL is a delay circuit whose delay time is longer than τma.

FIG. 5a is a circuit connection diagram, and the same figure is a time chart.

Problems to be Solved by the Invention As already shown in Figure 6, the access time of an actual memory element is considerably smaller than the worst value τmax determined by the specifications, assuming appropriate surrounding conditions. is normal. If DTAK is used in a time approximately equal to this actual access time,
When the signal returns, the data can be taken in immediately after it is output from the memory without making the CPU wait unnecessarily, and because it requires less waiting time, it is possible to perform more advanced processing.

Means to Solve the Problem In the present invention, since the DTAK signal is generated at a timing equal to the actual memory access time, a circuit is provided inside the memory device to check the access time and output this signal. That's what I do.

In order to check the actual access inside the device, there is a function that first detects the start of the access and outputs to the outside of the device that the access is in progress, and a signal that detects the completion of the access and indicates that the operation is in progress. It is necessary to have a function of resetting the internal operating state display signal), and the device is equipped with a circuit that has these two functions.

Function: The semiconductor memory device of the present invention is equipped with a circuit having the above-mentioned two types of functions, and can generate a signal that indicates the operating state inside the device, so by monitoring this signal outside the device,
The actual access time can be recognized by other external devices.

Embodiment FIG. 1 is a diagram showing an example of the basic configuration of a semiconductor memory device according to an embodiment of the present invention.

In FIG. 1, 1 is an address decoder, 2 is a memory cell, 3 is a dummy address decoder, 4 is a dummy word line memory cell, 6 is a dummy bit line memory cell, 6 is a dummy sense amplifier, 7 is a sense amplifier, and 8 is a dummy address decoder. Operation completion pulse line, 9 is an RS flip-flop, 11 is an operation start signal line,
12 is a start detection circuit, 13 is an address input signal terminal, 1
4 is an internal operation state display signal terminal, and 15 is a data output signal terminal.

There are two ways to initiate an access in a typical memory device. The first method is to change the element enable signal from disabled to enabled, and the address on the address input signal line at this time is accessed.

The second method is to change the address signal in the enabled state, and at this time access is started with the new address.

In either of these methods, one of the address or enable signals changes, so this change is first detected.

As a specific circuit, a change detection circuit as shown in FIG. 2a may be used. Inverter 2o in the figure is used as a delay element to obtain a delayed signal. The output of the exclusive OR circuit 21 generates a trigger-like pulse (the pulse width is equal to the delay time of the delay element) in response to a change of the input signal from 0" to "1" or from 1" to "o". do.

As for the enable signal, it is only necessary to detect the case of 0"→"1" (because in the case of "1"→"o",
(Since the device is in a disabled state, the entire device is inactive) Inverter 22. A simplified detection circuit consisting of an AND circuit 23 may also be used.

The operation start signal, that is, the access start signal, is valid only when the device is enabled, as shown in the circuit diagram in FIG. The logical sum circuit 26 performs a logical product of the total logical sum and the enable signal.

On the other hand, as methods for detecting the completion of an operation, the following two methods can be considered.

The first method is structurally the same as the original memory access (
Strictly defined, the structure should be the same as the worst access condition), consisting of a dummy part, that is, a dummy address decoder, a dummy word line, a dummy memory cell, a dummy bit line, and a dummy sense amplifier, and using the above operation start signal. and start accessing this dummy part. The time it takes for the operation start signal to propagate through the dummy portion and until some signal output is obtained from the dummy sense amplifier is equal to the worst access time. The structure of this dummy circuit is the shaded part in FIG.

The second method is to configure an operation completion detection circuit that observes the output of the original sense amplifier array and generates a pulse when all of them are in a determined state, without creating a dummy as described above. It is. FIG. 4a shows an example of the circuit configuration. The sense amplifier 28 connected to the memory cell 27 typically
When the operation is completed or not, it outputs an intermediate potential between 0" level and 1" level, so a comparator 29 that detects this intermediate value is connected to each sense amplifier output, and these comparator outputs are all It is a method that generates a pulse when a definite state is reached, a comparator 29 that detects an intermediate value, an AND circuit 3o that ANDs the outputs, and a change in the output of this AND circuit, especially 0''. →It consists of a change detection circuit 31 that detects a change of "1" and outputs a pulse.

The change detection circuit in FIG. 4a may be the same as that shown in FIG. 2b, for example. The input/output characteristics of the intermediate value detection comparator 29 are as shown in FIG. 4, and the output is "0" when the intermediate value is input, and the output is '1' at other times.

Finally, the internal operation status display signal that is output to the outside of the memory device must be output from the access operation start signal to the operation completion pulse, so it is realized using a set/reset flip-flop (RS flip-flop) circuit. . When the operation start pulse is input to the set terminal and the operation completion pulse set terminal, the output of this flip-flop becomes an internal operation state display signal, which is output to the outside of the device.

Effects of the Invention As described above, according to the present invention, the internal operation status display signal is
By outputting it outside the device, the actual memory access time can be monitored, and when configuring a computer system, the CPU side can use this signal as a DTAK signal, eliminating the need for unnecessary waiting time. This enables high-speed data processing.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing one embodiment of the semiconductor memory device of the present invention, FIGS. 2a and b are circuit diagrams showing two examples of change detection circuits constituting the device of this embodiment, and FIG. 3 4 is a circuit diagram of an access start signal generating circuit constituting the device of this embodiment, FIG. 4a is a circuit diagram showing a circuit for generating an operation completion pulse as another embodiment of the present invention, and FIG. An input/output characteristic diagram of an intermediate value detection comparator constituting the completion pulse generation circuit, Fig. 6a is a diagram showing an example of the configuration of a conventional computer system, and Fig. 5 is a time chart of each signal of the conventional computer system. It is. 1...Address decoder, 2...Memory cell, 3...Dummy address decoder, 4.
...Dummy word line memory cell, 5...
Dummy bit line memory cell, 6...Dummy sense amplifier, 7...Sense amplifier, 8...Operation completed pulse line, 9...RS flip-flop circuit , 11...Operation start signal line, 12...
...Start detection circuit, 13...Address input signal terminal, 14...Internal operation status display signal terminal, 15
...Data output signal terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person1-
1-Arshimata te"]-E 2--Me 7-C 3--1 ta "S-A 1"Sdicota 6--G S-
Lotato crystal for each 7--4-, 11. 11-i lower, on phase 9-1, δ7sy differential U 7° JAfl-fi explosion Mf target +2---j control L group billion 9th 13--A Y" reply input Blade name code 20.21 --- Inverter 26--Tori shield 8-way input power (high

Claims (4)

[Claims] (1) One of the multiple address input signals at the moment when the enable input signal that controls the operation of the entire device changes from the disabled state to the enabled state, or when the enable input signal maintains the enabled state. an operation start detection circuit that detects the moment when the memory changes and outputs an operation start signal; an operation completion detection circuit that detects the moment when the read and write operations as a memory are completed and outputs an operation completion signal; A semiconductor memory device comprising a flip-flop circuit set by an operation start signal and reset by the operation completion signal, and configured to output an output of the flip-flop circuit to the outside of the device as an internal operation state display signal. (2) The operation start detection circuit detects the exclusive OR of the state of each of the enable signal and the address signal a minute ago and the current state, the total OR of each exclusive OR output, the total OR, and the enable signal. Consists of a circuit network that takes the AND of signals.
2. The semiconductor memory device according to claim 1, wherein the AND output is used as an operation start signal. (3) The operation completion detection circuit is a dummy address decoder,
It consists of a dummy word line, a dummy memory cell, a dummy bit line, and a dummy sense amplifier, and this series of dummy circuit networks is accessed by an operation start detection signal,
2. The semiconductor memory device according to claim 1, wherein the output of the dummy sense amplifier is used as an operation completion detection signal. (4) The semiconductor memory device according to claim 1, wherein the operation completion detection circuit is a circuit that detects that all the outputs of a plurality of sense amplifiers are in a determined state and generates a detection pulse signal.