JPS62129838U - - Google Patents
Info
- Publication number
- JPS62129838U JPS62129838U JP1986016728U JP1672886U JPS62129838U JP S62129838 U JPS62129838 U JP S62129838U JP 1986016728 U JP1986016728 U JP 1986016728U JP 1672886 U JP1672886 U JP 1672886U JP S62129838 U JPS62129838 U JP S62129838U
- Authority
- JP
- Japan
- Prior art keywords
- output
- differential amplifier
- slice level
- input terminal
- optical signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003287 optical effect Effects 0.000 claims description 7
- 238000009499 grossing Methods 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 5
- 239000013307 optical fiber Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
- Dc Digital Transmission (AREA)
- Optical Communication System (AREA)
Description
第１図はこの考案による実施例の構成図、第２
図は光信号の送受信系統図、第３図は各種パター
ン信号の波形図、第４図は従来技術による第２図
の光／電気変換器４の回路図、第５図はスライス
レベルと差動増幅器１４の出力との関係図。
１……パターン発生器、２……電気／光変換器
、３……光フアイバケーブル、４……光／電気変
換器、５……出力端子、１１……増幅器、１２…
…コンデンサ、１３……バイアス回路、１４……
差動増幅器、１５〜１７……電源、１８……入力
端子、１９・２０……差動増幅器１４の入力端子
、２１……インバータ、２２……平滑回路、２３
……電源。
Figure 1 is a configuration diagram of an embodiment according to this invention, Figure 2
The figure shows an optical signal transmission/reception system diagram, Fig. 3 shows waveform diagrams of various pattern signals, Fig. 4 shows a circuit diagram of the conventional optical/electrical converter 4 shown in Fig. 2, and Fig. 5 shows slice level and differential signals. FIG. 4 is a relationship diagram with the output of the amplifier 14. DESCRIPTION OF SYMBOLS 1... Pattern generator, 2... Electrical/optical converter, 3... Optical fiber cable, 4... Optical/electrical converter, 5... Output terminal, 11... Amplifier, 12...
...Capacitor, 13...Bias circuit, 14...
Differential amplifier, 15-17...Power supply, 18...Input terminal, 19/20...Input terminal of differential amplifier 14, 21...Inverter, 22...Smoothing circuit, 23
……power supply.
Claims (1)
ン信号で変調された光信号を電気信号に変換し、
前記変換出力を直流カツトのコンデンサを通して
から前記変換出力に直流バイアスを加え、前記変
換出力を差動増幅器の第１の入力端子に加え、前
記差動増幅器の第２の入力端子にスライスレベル
を加え、前記各種パターン信号を復調する光信号
受信器において、 前記差動増幅器の出力をインバータに加え、前
記インバータ出力を平滑回路で整流し、前記平滑
回路出力を前記差動増幅器の第２の入力端子にス
ライスレベルとして加えることを特徴とする光信
号受信器のスライスレベル制御回路。[Claims for Utility Model Registration] Converting an optical signal modulated with various pattern signals with different combinations of "1" and "0" into an electrical signal,
The conversion output is passed through a DC cut capacitor, a DC bias is applied to the conversion output, the conversion output is applied to a first input terminal of a differential amplifier, and a slice level is applied to a second input terminal of the differential amplifier. , in the optical signal receiver that demodulates various pattern signals, the output of the differential amplifier is applied to an inverter, the inverter output is rectified by a smoothing circuit, and the smoothing circuit output is connected to a second input terminal of the differential amplifier. A slice level control circuit for an optical signal receiver, characterized in that a slice level is added to the signal as a slice level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986016728U JPH0427217Y2 (en) | 1986-02-07 | 1986-02-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986016728U JPH0427217Y2 (en) | 1986-02-07 | 1986-02-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62129838U true JPS62129838U (en) | 1987-08-17 |
| JPH0427217Y2 JPH0427217Y2 (en) | 1992-06-30 |
Family
ID=30808848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986016728U Expired JPH0427217Y2 (en) | 1986-02-07 | 1986-02-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0427217Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0385915A (en) * | 1989-08-30 | 1991-04-11 | Nec Corp | Automatic duty adjusting circuit |
-
1986
- 1986-02-07 JP JP1986016728U patent/JPH0427217Y2/ja not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0385915A (en) * | 1989-08-30 | 1991-04-11 | Nec Corp | Automatic duty adjusting circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0427217Y2 (en) | 1992-06-30 |
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