JPH0473213U - - Google Patents

Info

Publication number
JPH0473213U
JPH0473213U JP11524790U JP11524790U JPH0473213U JP H0473213 U JPH0473213 U JP H0473213U JP 11524790 U JP11524790 U JP 11524790U JP 11524790 U JP11524790 U JP 11524790U JP H0473213 U JPH0473213 U JP H0473213U
Authority
JP
Japan
Prior art keywords
voltage
control
circuit
low
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11524790U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11524790U priority Critical patent/JPH0473213U/ja
Publication of JPH0473213U publication Critical patent/JPH0473213U/ja
Pending legal-status Critical Current

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  • Continuous-Control Power Sources That Use Transistors (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図にこの考案の一実施例による電圧制御回
路を示す系統図、第2図はこの考案の他の一実施
例を電圧制御回路の系統図、第3図及び第4図は
第1及び第2図の基準電圧の作成を示す波形図、
第5図及び第6図は従来の電圧制御回路の系統図
である。 図において、1は三角波発生回路、2はコンパ
レータ、3は制御電圧、4は光トランスミツタ、
5は光フアイバー、6は光レシーバー、7は平滑
回路、8は電圧制御トランジスタ、9は直流電源
、10は増幅回路、11は分圧抵抗A、12は分
圧抵抗B、13は出力端子を示す。なお、図中、
同一符号は同一、又は相当部分を示す。
Fig. 1 is a system diagram showing a voltage control circuit according to one embodiment of this invention, Fig. 2 is a system diagram showing another embodiment of this invention. A waveform diagram showing the creation of the reference voltage in Figure 2,
FIGS. 5 and 6 are system diagrams of conventional voltage control circuits. In the figure, 1 is a triangular wave generation circuit, 2 is a comparator, 3 is a control voltage, 4 is an optical transmitter,
5 is an optical fiber, 6 is an optical receiver, 7 is a smoothing circuit, 8 is a voltage control transistor, 9 is a DC power supply, 10 is an amplifier circuit, 11 is a voltage dividing resistor A, 12 is a voltage dividing resistor B, 13 is an output terminal show. In addition, in the figure,
The same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 高圧にフローデイングした電源において、その
出力電圧を制御するための基準電圧を作る低圧側
の制御電圧発生回路と低圧側から高圧側に制御電
圧を伝達する回路と制御電圧を直流電圧にする直
流交換回路、その直流電圧を基準電圧として出力
電圧を制御する差動増幅回路とを備えた電圧制御
回路。
In a power supply that is flooded to high voltage, a control voltage generation circuit on the low voltage side that creates a reference voltage to control the output voltage, a circuit that transmits the control voltage from the low voltage side to the high voltage side, and a DC exchange that converts the control voltage into a DC voltage. A voltage control circuit that includes a circuit and a differential amplifier circuit that controls the output voltage using the DC voltage as a reference voltage.
JP11524790U 1990-10-31 1990-10-31 Pending JPH0473213U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11524790U JPH0473213U (en) 1990-10-31 1990-10-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11524790U JPH0473213U (en) 1990-10-31 1990-10-31

Publications (1)

Publication Number Publication Date
JPH0473213U true JPH0473213U (en) 1992-06-26

Family

ID=31863000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11524790U Pending JPH0473213U (en) 1990-10-31 1990-10-31

Country Status (1)

Country Link
JP (1) JPH0473213U (en)

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