JPS62128096A - Nonvolatile memory device - Google Patents

Abstract

PURPOSE:To lengthen the holding characteristic of the memory of a nonvolatile memory device far more than the holding characteristic of a memory single body by impressing the first prescribed sense voltage and the second and third sense voltages different by the constant voltage only in the upper and lower directions at the time of reading and rewriting the data when the reading data between them are different. CONSTITUTION:When the data are read, a sense voltage VGS is impressed to the memory transistor of the address of a memory array 11 corresponding to the given address input and a sense circuit 13 reads and outputs the condition of a memory. At such a time, simultaneously, a sense voltage VGS1 a little higher than VGS and a sense voltage VGS2 lower than it are impressed, the output at the time of respective sense voltages and the data at the time of impressing VGS are compared at memory data comparing circuit 16, and when at least one side of the data at the time of impressing the VGS1 or the VGS2 is different from the data at the time of the VGS, the output data at the time of impressing the VGS by a deleting and writing control circuit 15 are written. Thus, the data holding time of the memory can be extended.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile memory that can be electrically erased and written.

[Conventional technology]

Conventionally, MNOS (%etat-5iliconpit) has been used as nonvolatile memory that can be electrically erased and written.
r −1de −Si 1icor Adioxide
-5ilicon) memory is generally known.

The operating principle of MNOS memory is MOS (Meta-
9xide-di1licon)) A double film of silicon oxide film and silicon nitride film is used as the gate insulating film of the transistor, and the boundary between this double film is such that all the charges (carriers) are absorbed in the silicon nitride film in the vicinity. By accumulating, the threshold voltage of the transistor (threshold voltage)
1. Write down ten reports by changing. It's something that makes you happy.

As an example, a P-channel MOS memory will be described. When a constant drain voltage is applied to the memory transistor, the relationship between the gate voltage (VC) and the drain current (ID) is as shown in FIG. In Fig. 2, the lateral movement is the gate voltage (vG), the vertical axis is the drain current (ID), and the curve ■ is in the erased state, that is, when positive charges are expelled from the memory gate, it is a normal P-channel MOS transistor. The characteristics for the case where the threshold voltage VC and the total threshold voltage VC are present are shown below. Curve■
is a written state, that is, a characteristic when positive charges are accumulated in the insulating film of the memory gate, and the threshold voltage Vc of the MOS transistor is lower than Vc.

A basic memory read circuit is shown in FIG. 3. In FIG. 3, 41 is a memory transistor, 42 is a load resistor, 43 is a sense voltage application circuit, and 44 is a sense circuit.

Sense voltage V applied from the sense voltage application circuit 43
If a value is selected between vGl and Vc in FIG. 3, the transistor 41 is turned off during writing, and the voltage at point A in the diagram becomes the power supply voltage. - 10,000, when erasing, the transistor 41 is turned on (ON),
The voltage at point A is the value obtained by dividing the on-resistance (ROM) of the transistor 41 and the load resistance 42 (Rt, ),
If ROM<<RL is selected, it becomes Ov (ground potential).

The sense circuit 44 judges this voltage and outputs, for example, 1111 when the memory transistor 41 is written, and 10' when it is erased.

[Problem that the invention seeks to solve]

However, when the memory transistor 41 is in the write state, the charge accumulated in the gate insulating film does not change, but decreases over time, and the threshold voltage of the memory transistor is approaching the threshold voltage. When this exceeds the sense voltage Vcs', the state of the memory changes from 11g to 10'. The time required for the memory state to change from 11' to 10' is generally called data retention time, and is an essential characteristic of nonvolatile memory. To prevent such data loss, it is possible to constantly refresh the memory, but this type of memory has a limit on the number of times the data can be exchanged, and it is not possible to refresh the data indiscriminately.

On the other hand, even in the erased state, writing may be performed little by little because a sense voltage is applied to the memory gate when all reading is performed.
It is also possible that I changes to %1'.

Currently, the maximum retention time guaranteed in the market is 10 years, and it is said that it is difficult to guarantee a longer retention time in terms of manufacturing.

The present invention has been made to solve such problems, and an object of the present invention is to obtain a nonvolatile memory device that has a long retention time as a memory device even if the retention time of a single memory transistor is short.

[Means for solving problems]

The nonvolatile memory device according to the present invention applies a first sense voltage during normal data reading and second and third sense voltages that differ by a certain voltage above and below, and when the read data of both differs. It is a good idea to rewrite the data.

[For production]

When the threshold voltage changes by more than a certain value, refresh is performed to prevent data from being destroyed.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, 11 is a memory array, 12 is a sense voltage application circuit, 13 is a sense circuit, 14 is an address decoder, 15 is an erase/write control circuit, and 16 is a memory data comparison circuit.

First, when erasing all data, the word (wo) at the address of the memory array 11 corresponding to the given address input
All data in the memory (rd: word) is erased by the erase/write control circuit 15, and then %l is erased in the given data input.
Push F4F only into the l pit.

When reading data, a sense voltage (vcs) Th is applied to the memory transistor at the address in the memory array 11 corresponding to the given address input, and the sense circuit 13 reads and outputs the state of the memory.

At this time, a sense voltage VaS, which is slightly higher than VGS, and a sense voltage VasJr, which is lower, are applied at the same time, and the memory data is compared between the output when each sense pressure is applied and the data when Vcs'r is applied. Comparison L s in circuit 16
``c s + VGS'', when the data is small (when one side is different from the data when VCS is applied, erase/write control circuit 15, e) when applying Vcs' Write the output data 7i.

This allows the memory to be written to a threshold?
! By sensing when the pressure has approached the erased state or vice versa, and refreshing the memory, the data retention time of the memory can be extended.

Although the above embodiment describes an MNOS memory, the present invention can also be applied to other nonvolatile memory devices, such as nonvolatile memory devices using floating gates.

〔Effect of the invention〕

As explained above, according to the present invention, the second sense voltage differs by a certain voltage above and below from the predetermined first sense voltage during reading.
The retention characteristics of the memory of a non-volatile memory device are much longer than the retention characteristics of a single memory. It has the effect of being able to

In the case of No. 7, refreshing is performed only when absolutely necessary, so the problem of limiting the number of writes can be avoided.

[Brief explanation of drawings]

Figure 1 is a block diagram showing one embodiment of the present invention, Figure 2 is a diagram showing the relationship between the gate voltage and drain current of a memory transistor, and Figure 3 is a diagram showing an example of the configuration of a basic memory readout circuit. It is a circuit diagram. 11... Memory array, 12... Sense voltage application circuit, 13... Sense circuit, 14... Address decoder, 15... Erase/write control circuit, 16
...Memory data comparison circuit. Agent Masuo Oiwa Figure 1 Figure 2 VG VG2 VGS VGI Figure 3

Claims (1)

[Claims] It includes a nonvolatile memory element, a sense circuit that applies a sense voltage to the gate of the memory element to read the state of the memory, and a control circuit that controls erasing and writing of the memory element. A first sense voltage is applied to the gate of the memory element to perform a read operation, and a second sense voltage lower than the first sense voltage and a third sense voltage higher than the first sense voltage are applied to perform the read operation. When one of the values outputted from the sense circuit when the operation is performed and the second and third sense voltages are applied is different from the value output when the first sense voltage is applied, the first sense voltage is applied. A nonvolatile memory device characterized in that a value output when a sense voltage is applied is written into the memory element.