JPH04278298A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce malfunctions in writing/erasing operations due to a variation in a value of a high voltage power source and a stress to a memory cell in a flash EEPROM which is electromechanically written/erased by using a higher voltage power source than a power source voltage. CONSTITUTION:A high voltage power source 1 is used as a power source of a pulse generator 13 in which an output pulse depends on a power source voltage, and an output pulse width is varied in response to a variation in the high voltage power source.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor memory device.
In particular, the present invention relates to semiconductor nonvolatile memories that require a high voltage power source and can be electrically written or erased.

0002

[Prior Art] In recent years, flash EEPROM (
Electrically Erasable and
Programmable Read Only M
emory) are being commercialized by various companies. Its memory structure is an ultraviolet erasable EPROM (Erasable).
e and Electrically Progra
It is similar to mmable Read Only Memory), and can be erased electrically at once, so
It is attracting attention as an electrically writable/erasable floating volatile memory that has a lower bit cost than EEPROM.

An example of the circuit configuration of a conventional flash EEPROM during writing is shown in FIG. 2(a). In the figure, 10 is a floating gate type memory transistor whose gate is connected to the X decoder 7, 11 is a Y gate transistor whose gate is connected to the Y decoder 6, and 12 is a gate connected to the write circuit 5. A write transistor is shown.

[0004] Also, 1 is a 5V power supply usually called VCC, and 2 is a high voltage power supply usually called VPP.
Requires about 2V. And 3 is the above VCC/VPP
This is the output of the VCC/VPP switching circuit 8 which switches and outputs the VCC/VPP switching circuit 8.
This is the power supply for the VPP during writing/erasing.
level, and becomes VCC level when reading. 4 is the output of the pulse generator 13. The pulse generator 13 uses the VCC power supply 1 as its power supply, and is constructed using an insulated gate transistor. The pulse width of the pulse output from the pulse generator 13 is dependent on the power supply voltage, and has a characteristic that it becomes shorter when the power supply voltage VCC is high, and becomes longer when the power supply voltage is low.

FIG. 2(b) shows a timing chart for writing as an example. However, the outputs of the Y decoder 6 and write circuit 5 are omitted here. First, when writing to the memory 10, it is necessary to apply a high voltage power supply VPP to the write circuit 5, X decoder 7, and Y decoder 6.
Since it is configured to use the power source as the power source, it has the characteristic that even if VPP changes (for example, VPP and VPP' in the figure), the pulse width does not change.

On the other hand, when looking at the characteristics of the memory 10 itself during writing, there is a dependence on the high voltage power supply VPP, as shown in FIG. In the figure, the horizontal axis represents the pulse width (t), and the vertical axis represents the threshold value (VTH) of the memory transistor 10. When writing is performed, the threshold value VTH changes and becomes larger, but the rate of change is dependent on the high voltage power supply VPP, and becomes faster as the high voltage power supply VPP is larger. If VP is the write determination level at which writing is considered complete, a pulse width of tP is required when the high voltage power supply is VPP, and a pulse width of tP' is required when the high voltage power supply is VPP'. Here, VPP>VPP', and then the relationship between the pulse widths is tP<tP'.

Furthermore, when erasing, as shown in FIG.
When erasing is performed, the threshold value VTH of the memory transistor 10 first changes and becomes smaller, but the rate of change becomes faster as the high voltage power supply VPP increases. If VE is the erase determination level at which erasing is considered complete, then a pulse width of tE is required when the high voltage power source is VPP, and a pulse width of tE' is required when the high voltage power source is VPP'. Here VPP>V
PP', and the pulse width relationship at that time is tE < tE
'.

[0008]

[Problems to be Solved by the Invention] The conventional semiconductor memory device is constructed as described above, and the pulse generator The pulse width output from the high voltage power supply VP remains constant even if the high voltage power supply VPP changes.
When P becomes low, write (erase) failures tend to occur, and conversely, when high voltage power supply VPP becomes high, memory elements deteriorate more quickly due to overstress.

The present invention was made to solve the above-mentioned problems, and its purpose is to provide a semiconductor memory device that can perform stable writing (erasing) regardless of fluctuations in the high voltage power supply VPP. shall be.

0010

[Means for Solving the Problems] A semiconductor memory device according to the present invention uses a high voltage power source as a power source for a pulse generator, automatically shortens the pulse width when the high voltage power source VPP is high, and automatically shortens the pulse width when the high voltage power source VPP is low. The pulse width is made longer.

[0011]

[Operation] In this invention, since a high voltage power source is used as the power source of the pulse generator, the output pulse width is short when the voltage is high and becomes long when the voltage is low due to its voltage dependence. Stable writing (erasing) can be performed on the data.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1(a), the same symbols as in FIG. 2(a) indicate the same or corresponding parts, and the difference from FIG. 2(a) is that the high voltage power supply VPP2 is used as the power source for the pulse generator 13.
This is because we used

Next, the operation will be explained. Figure 1(b)
shows a timing chart during writing, and as can be seen from this figure, the high voltage power supply VPP applied becomes lower due to the voltage dependence of the pulse generator 13, and when it reaches VPP', the pulse width of the pulse generator becomes longer (tvPP). ), and accordingly, the write circuit 5,X is automatically connected to the subsequent stage.
The high voltage application time of the decoder 7 and Y decoder 6 becomes longer. Conversely, when the high voltage power supply VPP increases, the pulse width automatically becomes shorter (tvPP').

Therefore, when the high voltage power supply VPP becomes low, the pulse width is automatically lengthened, and when VPP becomes high, the pulse width is automatically shortened, reducing the stress on the memory cells due to fluctuations in the power supply voltage. is reduced.

In the above embodiment, the operation at the time of writing has been explained, but the same effect can be obtained at the time of erasing. That is, the high voltage power supply V is used as the power supply for the pulse generator 13.
By using PP, when the high voltage power supply VPP is increased, the pulse width is automatically shortened, and when VPP is decreased, the pulse width is automatically lengthened, so that stable erasing is possible.

[0016]

As described above, according to the semiconductor memory device of the present invention, by using the high voltage power supply VPP as the power source of the pulse generation circuit, high voltage can be obtained with a simple configuration without adding any particular circuit. Even when the power supply VPP fluctuates, stable writing/erasing can be performed, and deterioration of memory cells due to overstress can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram and a chart showing operation timing of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a chart showing a circuit configuration diagram and operation timing of a conventional semiconductor memory device.

FIG. 3 is a diagram for explaining write characteristics of semiconductor memory devices according to the prior art and the present invention, using a high voltage power supply VPP as a parameter.

FIG. 4 is a diagram for explaining erase characteristics of semiconductor memory devices according to the prior art and the present invention using a high voltage power supply VPP as a parameter.

[Explanation of symbols]

1 Power supply voltage VCC 2 High power supply voltage VPP 3 VCC/VPP switching circuit output 4 Pulse generator output 5 Write circuit 6 Y decoder 7 X decoder 8 VCC/VPP switching circuit 9 Sense amplifier 10 Floating gate type memory transistor 11 Y gate transistor 12 Write transistor 13 Pulse generator

Claims (2)

[Claims] 1. A nonvolatile semiconductor memory device that requires a high voltage power supply for writing or erasing memory and is equipped with a pulse generation circuit that generates pulses for writing or erasing, wherein the power supply for the pulse generation circuit is A semiconductor memory device characterized in that the above-mentioned high voltage power supply is used as a semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the memory is composed of an insulated gate transistor having a floating gate.