JPS62126662A - Constant current circuit - Google Patents
Constant current circuitInfo
- Publication number
- JPS62126662A JPS62126662A JP60267730A JP26773085A JPS62126662A JP S62126662 A JPS62126662 A JP S62126662A JP 60267730 A JP60267730 A JP 60267730A JP 26773085 A JP26773085 A JP 26773085A JP S62126662 A JPS62126662 A JP S62126662A
- Authority
- JP
- Japan
- Prior art keywords
- fet
- gate
- drain
- constant current
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Control Of Electrical Variables (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は定電流回路に関し、特に、抵抗値を制御する事
により定電流値を可変する事を可能にした定電流回路に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a constant current circuit, and more particularly to a constant current circuit that makes it possible to vary a constant current value by controlling a resistance value.
小型電子腕時計、電子卓上計算機等に用いられる集積回
路装置は、集積回路装置の外部から供給される電源を一
旦昇圧回路あるいは降圧回路を介して昇圧もしくは降圧
して供給する方式をとっている。この電源供給方式の場
合外部の電力供給装置の電源変動が直接集積回路に影響
し、集積回路の動作を不安定にする。BACKGROUND ART Integrated circuit devices used in small electronic wristwatches, electronic desk calculators, and the like employ a system in which power supplied from outside the integrated circuit device is first boosted or stepped down through a boost circuit or step-down circuit before being supplied. In this power supply system, power fluctuations from an external power supply device directly affect the integrated circuit, making the operation of the integrated circuit unstable.
以上の点を顧み、近年の集積回路装置は第2図に示すよ
うな定電圧電、源を内蔵する方式が多く利用されている
。すなわち外部から供給される市、圧VDDとVssと
の差電圧で定電流回路lを駆動しこの定電流回路1の電
流を電流−電圧変換回路2に流し、該変換回路2に得ら
れる電圧を安定化回路3で安定化して出力端子4に定電
圧出力を得ている。Considering the above points, many integrated circuit devices in recent years have a built-in constant voltage power source as shown in FIG. 2. That is, the constant current circuit 1 is driven by the voltage difference between the voltage VDD and Vss supplied from the outside, and the current of the constant current circuit 1 is passed through the current-voltage conversion circuit 2, and the voltage obtained in the conversion circuit 2 is It is stabilized by the stabilizing circuit 3 and a constant voltage output is obtained at the output terminal 4.
しかし集積回路装置に内蔵された定電圧電源の基準電流
を作る定電流回路は、構成するトランジスタ、抵抗、ダ
イオード等の素子特性により一義的に電流値が決められ
てしまい、集積回路装置を製造した後に定電流回路の電
流値を変えることができない。あらかじめ集積回路の外
部に可変抵抗器等を設けて電流値を可変することは可能
であるが、これでは外付菓子の増加をきたし、小型電子
腕時計、電子卓上計算機等の実装密度が高い装置では極
めて不利となる。更に、部品コストや製造上で調整工程
が必要となりコストアップにつながる。However, in the constant current circuit that creates the reference current of the constant voltage power supply built into the integrated circuit device, the current value is uniquely determined by the characteristics of the constituent transistors, resistors, diodes, etc., and it is difficult to manufacture the integrated circuit device. It is not possible to change the current value of the constant current circuit afterwards. It is possible to vary the current value by installing a variable resistor etc. outside the integrated circuit in advance, but this increases the number of external devices and is not suitable for devices with high packaging density such as small electronic wristwatches and electronic desk calculators. This will be extremely disadvantageous. Furthermore, an adjustment process is required for component costs and manufacturing, leading to an increase in costs.
本発明の定電流回路は、第1の電源を第10導電形の第
1のIG−FETのソースに接続し、該第1のIG−F
ETのゲート及びドレインを第2の導電形の第2のIG
−FETのドレイン及び第1の導電型の第3のIG−F
E’rのゲートに接続し、該第3のIG−FE’rのド
レインを第2の導電型の第4のIG−FETのゲートと
ドレイン及び前記第2のIG−FETのゲートに接続し
、該第2のIG−FETのソース及び前記第4のIG−
FETのソースを第2の電源に接続し、前記第3のI
G −F E jI’のソースを抵抗の一端に接続し、
該抵抗の他端を前記第1の電源に接続する定電流回路に
おいて、前記抵抗を少なくとも2個以上の複数個の直列
接続で構成し、該直列接続した抵抗の各々に並列に第1
の導電形の第5のTG−FETを接続し該l0−F’E
’rのゲートに選択的に導通させるようにした信号を入
力することを特徴とする。The constant current circuit of the present invention connects a first power source to the source of a first IG-FET of a tenth conductivity type, and
The gate and drain of the ET are connected to a second IG of a second conductivity type.
- the drain of the FET and the third IG-F of the first conductivity type;
E'r, and the drain of the third IG-FE'r is connected to the gate and drain of the fourth IG-FET of the second conductivity type and the gate of the second IG-FET. , the source of the second IG-FET and the fourth IG-FET
The source of the FET is connected to a second power supply, and the third I
Connect the source of G −F E jI′ to one end of the resistor,
In a constant current circuit in which the other end of the resistor is connected to the first power source, the resistor is configured by connecting at least two or more resistors in series, and a first resistor is connected in parallel to each of the series-connected resistors.
A fifth TG-FET of conductivity type is connected to the l0-F'E
It is characterized by inputting a signal which selectively makes the gate of 'r conductive.
以下に図面を用いて本発明をよシ詳細に説明する。第1
図は本発明の一実施例を示丈基準電流を発生させるPチ
ャンネルの絶縁ゲート型電界効果トランジスタ(IG−
FET)のソース及び基準電流を制御する抵抗R1の一
端を外部から供給される第1の電源VDDに接続し抵抗
R1の他端には抵抗Rnまで抵抗を直列に接続し抵抗R
nの他端をPチャンネルのIG−FET22のソースに
接続スる。抵抗R1〜Rnの一端には各々Pチャンネル
のIG−FET11〜Inのソースを接続し抵抗R1〜
Rnの抵抗の他端にはIG−pE’rtl〜1nのドレ
インを各々接続する。前記IG−FET21のゲート及
びドレインをIG−FET22のゲート及びNチャンネ
ルのIG−FET31のドレインに接続しこのIG−F
ET31のゲートをNチャンネルのIG−FET32の
ゲート及びドレイン及びIG−FET22のドレインに
接続しIG−PE’r31,32のソースを第2の電源
Vs+sに接続する。IG−FET11〜Inのゲート
に制御信号11〜Inを各々入力し、各制御信号に低電
位レベル(以下−J、 aと称する)を与えると、IG
−FETI 1〜1 nが導通状態(以下1ON1と称
する)になり、ONのIG−FETII〜1nと対にな
っている抵抗R1〜Rnの抵抗値1’1%rnを選択的
にゼロにする事が出来る。即ちIG−FB’l”22の
ソースと第1の電源VDDとの間にある抵抗値(h 1
+ r、2十・・・+rn)を変化する事ができ、定
電流10は次式で表わされる。The present invention will be explained in detail below using the drawings. 1st
The figure shows one embodiment of the present invention, a P-channel insulated gate field effect transistor (IG-
One end of the resistor R1 that controls the source and reference current of the resistor R1 is connected to the first power supply VDD supplied from the outside, and the other end of the resistor R1 is connected in series up to the resistor Rn.
The other end of n is connected to the source of the P channel IG-FET 22. The sources of the P-channel IG-FETs 11-In are connected to one ends of the resistors R1-Rn, respectively, and the resistors R1-Rn are
The drains of IG-pE'rtl to 1n are connected to the other end of the resistor Rn, respectively. The gate and drain of the IG-FET 21 are connected to the gate of the IG-FET 22 and the drain of the N-channel IG-FET 31.
The gate of ET31 is connected to the gate and drain of N-channel IG-FET32 and the drain of IG-FET22, and the sources of IG-PE'r31 and 32 are connected to the second power supply Vs+s. When control signals 11 to In are input to the gates of IG-FETs 11 to In, and a low potential level (hereinafter referred to as -J, a) is applied to each control signal, the IG
-FETI 1~1n becomes conductive (hereinafter referred to as 1ON1), and the resistance value 1'1%rn of the resistors R1~Rn paired with ON IG-FETII~1n is selectively zeroed. I can do things. That is, the resistance value (h 1
+r, 20...+rn), and the constant current 10 is expressed by the following equation.
ここで、qは電子の電荷、kはボンラマン定数、Tは絶
対温度、m21.m22.m31.m32はそれぞれI
G−FET21,22,31.32のチャンネル寸法比
(チャンネル幅/チャンネル長)で表わされる定数であ
る。Here, q is the electron charge, k is the Bon-Raman constant, T is the absolute temperature, and m21. m22. m31. m32 is each I
This is a constant expressed by the channel size ratio (channel width/channel length) of G-FETs 21, 22, 31, and 32.
集積回路装置の内部に持っている配憶回路等の論理出力
を制御信号111〜Ilnに与える事により記憶回路等
の状態に応じた定電流を得る事ができる。By applying the logical outputs of the storage circuits, etc. inside the integrated circuit device to the control signals 111 to Iln, it is possible to obtain a constant current according to the state of the storage circuits, etc.
小型腕時計や電子卓上計算機を組み立てた後に所定の記
憶回路の内容を更新することにより容易に定電流値を可
変する事が可能になる。By updating the contents of a predetermined memory circuit after assembling a small wristwatch or electronic desktop calculator, it becomes possible to easily vary the constant current value.
制御信号Ill〜Ilnを集積回路装置の内部に持つ配
憶回路等から与える代りに、集積回路装置に入力端子を
設けることにより外部から信号を加え前記制御信号■1
1〜Ilnにm Lwを与える事により定電流回路の電
流値を可変できることは言うまでもない。Instead of giving the control signals Ill to Iln from a storage circuit or the like inside the integrated circuit device, input terminals are provided in the integrated circuit device so that signals are added from the outside and the control signals (1)
It goes without saying that the current value of the constant current circuit can be varied by giving m Lw to 1 to Iln.
尚、実施例ではT O−F ET 11〜I nをPチ
ャンネル形P E jrで説明したが、抵抗R1〜’R
nをIG−FET31のソースと第2の電源Vsgの間
に挿入しIG−FET22のソースを第1の電源のVD
Dに接続し、抵抗に並列に接続するFETをNチャンネ
ル形FETとし、該FE’[’のゲートに制御信号に入
力し、制御信号に高電位を与える事により同様の効果が
得られる事は明白である。Incidentally, in the embodiment, T O-FET 11 to I n were explained as P channel type P E jr, but the resistors R1 to 'R
n is inserted between the source of IG-FET 31 and the second power supply Vsg, and the source of IG-FET 22 is connected to VD of the first power supply.
The same effect can be obtained by making the FET connected to D and connected in parallel to the resistor an N-channel FET, inputting the control signal to the gate of the FE'[', and applying a high potential to the control signal. It's obvious.
本発明によれば、外部から与えらhる電源で駆動される
定電流回路中の抵抗値を制御信号により任意に選択でき
、定電流値を可変する事のできる定電流回路を実現でき
る。According to the present invention, the resistance value in a constant current circuit driven by an externally applied power source can be arbitrarily selected by a control signal, and a constant current circuit capable of varying the constant current value can be realized.
第1図は本発明の一実施例の回路図、第2図は従来例の
定電流回路を含む集積回路装置を示すブロック図である
。
11〜I n 、 21 、22−+m+pチャ7ネル
IG−P E T、 31 、32・・−・−・N−t
r ンネルIG−FE’[’。
■1〜In・・・・・・制御信号、R1−Rn・・・・
・・抵抗。FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a block diagram showing an integrated circuit device including a conventional constant current circuit. 11~In, 21, 22-+m+p channel 7 channel IG-PET, 31, 32...--N-t
r channel IG-FE'['. ■1~In...Control signal, R1-Rn...
··resistance.
Claims (1)
スに接続し、該第1のIG−FETのゲート及びドレイ
ンを第2の導電形の第2のIG−FETのドレイン及び
第1の導電型の第3のIG−FETのゲートに接続し、
該第3のIG−FETのドレインを第2の導電型の第4
のIG−FETのゲートとドレイン及び前記第2のIG
−FETのゲートに接続し、該第2のIG−FETのソ
ース及び前記第4のIG−FETのソースを第2の電源
に接続し、前記第3のIG−FETのソースを抵抗の一
端に接続し、該抵抗の他端を前記第1の電源に接続する
定電流回路において、前記抵抗を少なくとも2個以上の
複数個の直列接続で構成し、該直列接続した抵抗の各々
に並列に第1の導電形の第5のIG−FETを接続し該
IG−FETのゲートに選択的に導通させるようにした
信号を入力することを特徴とする定電流回路。A first power source is connected to the source of a first IG-FET of a first conductivity type, and the gate and drain of the first IG-FET are connected to the drain and drain of a second IG-FET of a second conductivity type. connected to the gate of the third IG-FET of the first conductivity type;
The drain of the third IG-FET is connected to the fourth IG-FET of the second conductivity type.
The gate and drain of the IG-FET and the second IG-FET
- connected to the gate of the FET, the source of the second IG-FET and the source of the fourth IG-FET connected to a second power supply, and the source of the third IG-FET connected to one end of the resistor; and the other end of the resistor is connected to the first power source. 1. A constant current circuit, characterized in that a fifth IG-FET of one conductivity type is connected to the gate of the IG-FET, and a signal is input to selectively conduct the gate of the IG-FET.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60267730A JP2507309B2 (en) | 1985-11-27 | 1985-11-27 | Constant current circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60267730A JP2507309B2 (en) | 1985-11-27 | 1985-11-27 | Constant current circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62126662A true JPS62126662A (en) | 1987-06-08 |
JP2507309B2 JP2507309B2 (en) | 1996-06-12 |
Family
ID=17448770
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60267730A Expired - Lifetime JP2507309B2 (en) | 1985-11-27 | 1985-11-27 | Constant current circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2507309B2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5799217U (en) * | 1980-12-08 | 1982-06-18 | ||
JPS5992910U (en) * | 1982-12-09 | 1984-06-23 | 日産自動車株式会社 | constant current circuit |
-
1985
- 1985-11-27 JP JP60267730A patent/JP2507309B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5799217U (en) * | 1980-12-08 | 1982-06-18 | ||
JPS5992910U (en) * | 1982-12-09 | 1984-06-23 | 日産自動車株式会社 | constant current circuit |
Also Published As
Publication number | Publication date |
---|---|
JP2507309B2 (en) | 1996-06-12 |
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