JPS62123889A - High speed channel - Google Patents

High speed channel

Info

Publication number
JPS62123889A
JPS62123889A JP26433885A JP26433885A JPS62123889A JP S62123889 A JPS62123889 A JP S62123889A JP 26433885 A JP26433885 A JP 26433885A JP 26433885 A JP26433885 A JP 26433885A JP S62123889 A JPS62123889 A JP S62123889A
Authority
JP
Japan
Prior art keywords
waveform distortion
communication path
switch
distortion compensation
speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26433885A
Other languages
Japanese (ja)
Inventor
Kunio Nagashima
長島 邦雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP26433885A priority Critical patent/JPS62123889A/en
Publication of JPS62123889A publication Critical patent/JPS62123889A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a channel of low power consumption and low cost without requiring many waveform compensating circuits by providing a waveform distortion compensating means that compensates the waveform distortion generated in the channel between optional switch steps. CONSTITUTION:Waveform distortion compensating circuits 109, 110, 111, 112 are provided between a secondary switch 405 and a tertiary switch 408. For instance, when a path from an incoming line 413 to an outgoing line 419 is looked at, the waveform distortion compensating circuit 112 compensates the waveform distortion between the incoming line 413 and the outgoing line 100 of a grid switch 404. Waveform distortion compensating circuits 309-312 are optimal designed for bit rate of 100Mb/s, and 323-326 are for 800Mb/s. Thus, a waveform distortion compensating circuit corresponding to respective signal speed can be selected at the time of path selection.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は高速通話路、特に高速ディジタル信号の交換を
行なう空間背割形高速通話路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed communication path, and more particularly to a space-back type high-speed communication path for exchanging high-speed digital signals.

(従来の技術〕 現在、音声、データを中心とする各種通信サービスを一
元的に提供するディジタル総合サービス細(ISDN)
の構築が進められている。しかしながら、近年情報化社
会の進展に伴い従来の音声。
(Conventional technology) Currently, integrated digital service networks (ISDN) provide a variety of communication services centered on voice and data.
construction is underway. However, in recent years, with the advancement of the information society, the traditional voice has changed.

データに加えて超高速データ、ファクシミリ、高精細静
止面から動画、高精細動画に到る極めて広範なサービス
の要求が高まりつつある。
In addition to data, there is a growing demand for an extremely wide range of services, including ultra-high-speed data, facsimile, and high-definition still images to video and high-definition video.

このような信号をディジタル符号化すると、従来の音声
、データの64 K b / sに比し1.5Mb、/
s以上800 M b / s程度までと極めて広範で
高速なビットレートとなり、この為上記の高速ディジタ
ル信号を交換する交換機には主として空間分割形通話路
が用いられる。しかしながら、このような高速ディジタ
ル信号の交換を行なう交換機においては、伝送路のみな
らず交換機の通話路において生ずる波形歪が大きな問題
となる。
When such a signal is digitally encoded, the speed is 1.5 Mb/s, compared to 64 Kb/s for conventional voice and data.
The bit rate is extremely wide and high, ranging from 100 Mb/s to about 800 Mb/s, and for this reason, space-division communication channels are mainly used in exchanges for exchanging the above-mentioned high-speed digital signals. However, in exchanges that exchange such high-speed digital signals, waveform distortion occurring not only in the transmission path but also in the communication path of the exchange poses a major problem.

この高速通話路の構成法としては、例えば電子通信学会
技術報告5B83−105 r広帯域通話路構成法に関
する考案j俵寛二池に記載されているものが知られてい
る。
As a method of configuring this high-speed communication path, for example, the method described in IEICE technical report 5B83-105 r Ideas for Configuring Wideband Communication Path J Tawara Kanjiike is known.

第4図は従来技術による高速通話路の一例を示す。第4
図に示した高速通話路は400.401を陰む入線数n
、出線数tのl(個の格子スイッチによって構成される
一次スイッチ402と、403.404を含む入線数に
、出線数Sのt個の格子スイッチによって構成される二
次スイッチ405と、406; 407を含む入線数t
、出線数mの5個の格子スイッチによって構成される三
次スイッチ408と、三次スイッチの出線に設けられた
409,410,411.412を含むms個の波形歪
補償回路とによって構成されている。
FIG. 4 shows an example of a high-speed communication path according to the prior art. Fourth
The high-speed communication path shown in the figure has a number of incoming lines n that is below 400.401.
, a primary switch 402 composed of l() lattice switches with a number of outgoing lines t, and a secondary switch 405 composed of t lattice switches with an incoming line number S including 403 and 404, 406; Number of incoming lines t including 407
, a tertiary switch 408 constituted by five lattice switches with m outgoing lines, and ms waveform distortion compensation circuits including 409, 410, 411, and 412 provided at the outgoing lines of the tertiary switch. There is.

第4図において、−次スイッチ402と二次スイッチ4
05.二次スイッチ405と三次スイ・・lチ408と
の間は互いにそれぞれリンク接続されており、413,
414,415.416を含むn k本の入線と41’
7,418,419,420を含むIn S本の入線と
の間を任意に接続することができる。
In FIG. 4, the -order switch 402 and the secondary switch 4
05. The secondary switch 405 and the tertiary switch 408 are linked to each other, and 413,
nk incoming lines including 414, 415, 416 and 41'
In S incoming lines including 7,418,419,420 can be arbitrarily connected.

第4図には、格子スイッチ400,404,407によ
って、入ff1413と出線419との間を接続した例
を示す1通話信号のピットレー1−が高速になってくる
と、入線413と出線421間の配線で生ずる表皮効果
、誘電体損失、また入線413と出線421間に含まれ
るスイッチ素子の周波数特性等の影響により信号に波形
歪が生じ、これが高速通話路における符号誤りが生ずる
原因となる。この為、第4図に示した高速通話路におい
ては、三次スイッチ408のすべての出線に409.4
10,411.412を含むms個の波形歪補償回路を
設け、通話信号の再生を行っている。
FIG. 4 shows an example in which the input FF 1413 and the output line 419 are connected by the grid switches 400, 404, 407. When the pit-ray 1- of one call signal becomes high speed, the input line 413 and the output line 419 are connected. Waveform distortion occurs in the signal due to the effects of the skin effect and dielectric loss occurring in the wiring between the input line 413 and the output line 421, and the frequency characteristics of the switching element included between the input line 413 and the output line 421, which is the cause of code errors in high-speed communication paths. becomes. Therefore, in the high-speed communication path shown in FIG. 4, all outgoing lines of the tertiary switch 408 are
A number of waveform distortion compensation circuits including 10,411,412 ms are provided to reproduce the call signal.

第5図は第4図に示した波形歪補償回路409゜410
.411,412の第1の具体例を示す。
Figure 5 shows the waveform distortion compensation circuit 409°410 shown in Figure 4.
.. A first specific example of 411 and 412 will be shown.

第5図によれば第4図に示した波形歪補償回路409.
410,411.412は入力に波形歪が生じたディジ
タル信号が加えられた等化増幅器500と、該等化増幅
器500の出力に入力を接続されたタイミング回路50
1と、等化増幅器500の出力にデータ入力502を、
タイミング回路501の出力にクロック人力503をそ
れぞれ接続された識別再生回路504とを含む。
According to FIG. 5, the waveform distortion compensation circuit 409 shown in FIG.
410, 411, and 412 are an equalizing amplifier 500 to which a digital signal with waveform distortion is added, and a timing circuit 50 whose input is connected to the output of the equalizing amplifier 500.
1 and a data input 502 to the output of the equalizing amplifier 500,
It includes an identification/reproduction circuit 504 connected to a clock input 503 to the output of the timing circuit 501, respectively.

第5図において等化増幅器500は第4図に示した入線
413から出線421に到る径路で減衰を受けた高域成
分を相対的に増幅することにより、入力信号を識別に適
した波形に整形し識別再生回路504のデータ人力50
2とタイミング回路501の入力に加える。タイミング
回路501はこのようにして得られた信号の中からクロ
ック周波数成分を抽出し、細いパルス列に変換して、識
別再生回路504のクロ・シフ人力503に送出する。
In FIG. 5, the equalizing amplifier 500 converts the input signal into a waveform suitable for identification by relatively amplifying the high-frequency components that have been attenuated along the path from the input line 413 to the output line 421 shown in FIG. The data human power 50 of the identification reproduction circuit 504 is formatted into
2 and the input of the timing circuit 501. The timing circuit 501 extracts the clock frequency component from the signal obtained in this way, converts it into a thin pulse train, and sends it to the clock shifter 503 of the identification and reproduction circuit 504.

識別再生回路504はデータ入力502に加えられた信
号をクロック人力503に加えられたクロック信号に同
期して°゛1”であるか、0°′であるかを識別して、
信号波形の再生を行なう。
The identification/reproduction circuit 504 identifies whether the signal applied to the data input 502 is '1'' or 0°' in synchronization with the clock signal applied to the clock input 503.
Plays back the signal waveform.

このような波形歪補償回路としては例えば産報出版株式
会社刊、金子尚志著rPCM通信の技術」第63頁記載
の再生中継器回路を適用することができる。
As such a waveform distortion compensation circuit, for example, a regenerative repeater circuit described in "Techniques of rPCM Communication" by Takashi Kaneko, published by Sanpo Publishing Co., Ltd., page 63 can be applied.

第6図は第4図に示した波形歪補償回路409゜410
.411,412の第2の具体例を示す。
Figure 6 shows the waveform distortion compensation circuit 409°410 shown in Figure 4.
.. A second specific example of 411 and 412 will be shown.

第6図において第5図と同一番号を付したものは第5図
と同一の構成要素を示す。
In FIG. 6, the same numbers as in FIG. 5 indicate the same components as in FIG.

第6図において等化増幅器500は、第5図に示した第
1の具体例と同様に、第4図に示した入線413から出
線421に到る径路で減衰を受けた高域成分を相対的に
増幅し、再生回路604の入力に送出する。再生回路6
04はこのようにして得られた信号をあらかじめ定めら
れた閾値と比較することにより1゛°であるか、0°゛
であるかを識別して信号波形の再生を行なう。
In FIG. 6, equalizing amplifier 500, similar to the first specific example shown in FIG. It is relatively amplified and sent to the input of the regeneration circuit 604. Regeneration circuit 6
04 identifies whether the signal is 1° or 0° by comparing the signal thus obtained with a predetermined threshold and reproduces the signal waveform.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、第4図に示した従来技術による高速通話
路においては、合計量s%もの波形歪補償回路を必要と
し、これが通話路の消費電力コストの増大を招いていた
。また第5図、第6図に示した波形歪補償回路において
、等化増幅器500゜タイミング回路501等はいずれ
もあらかじめ定められた信号速度に最適に設計されてい
ることが多く、この為1.5Mb、/s〜800 M 
b / sに及ぶ広範なビットレートを有する種々のメ
ディア°を交換することは不可能であった4 本発明の目的は、多くの波形歪補償回路を必要ヒせず、
低消費電力、低価格の高速通話路を提供することにある
However, the high-speed communication path according to the prior art shown in FIG. 4 requires waveform distortion compensation circuits with a total amount of s%, which causes an increase in the power consumption cost of the communication path. Furthermore, in the waveform distortion compensation circuits shown in FIGS. 5 and 6, the equalizing amplifier 500° timing circuit 501, etc. are often designed optimally for a predetermined signal speed, and for this reason, 1. 5Mb,/s~800M
It has been impossible to interchange various media with a wide range of bit rates ranging up to 1000 b/s.
The objective is to provide a high-speed communication path with low power consumption and low cost.

更に本発明の目的は広範なビ・ソトレートを有する種々
のメディアを交換することが可能な高速通話路を提供す
ることにある。
It is a further object of the present invention to provide a high speed communication path capable of exchanging a variety of media having a wide range of bi-sotorates.

〔問題点を解決するための手段〕[Means for solving problems]

水弟1の発明によれば複数の格子スイッチを多段に接続
して構成される通話路において、任意のスイッチ段間に
面記通話路において生ずる波形歪を補償する波形歪補償
手段を備えることを特徴とする高速通話路が得られる。
According to the invention of Mizui 1, in a communication path formed by connecting a plurality of grid switches in multiple stages, waveform distortion compensating means for compensating for waveform distortion occurring in the surface communication path is provided between arbitrary switch stages. A characteristic high-speed communication path can be obtained.

水弟2の発明によると複数の格子スイッチを多段に接続
して構成される通話路において、任意のスイッチ段間に
前記通話路において生ずる波形歪を補償する波形歪補償
手段を信号速度に応じて複数個設け、径路設定時に前記
信号に応じた波形歪補償手段を選択する手段を備えるこ
とを特徴とする高速通話路が得られる。
According to the invention of Mizui 2, in a communication path formed by connecting a plurality of grid switches in multiple stages, a waveform distortion compensating means for compensating for waveform distortion occurring in the communication path is provided between arbitrary switch stages according to the signal speed. A high-speed communication path is obtained, which is characterized in that a plurality of such devices are provided and means is provided for selecting a waveform distortion compensating device according to the signal at the time of route setting.

更に水弟3の発明によると複数の格子スイッチを多段に
接続して構成される通話路において、任意のスイッチ段
間に前記通話路において生ずる波形歪を補償する波形歪
補償手段を信号速度に応じてそれぞれ互いに異なる径路
に複数個設け、径路設定時に前記信号速度に応じた波形
歪補償手段を含む径路を選択する手段を備えることを特
徴とする高速通話路が得られる。
Furthermore, according to the invention of Mizui 3, in a communication path formed by connecting a plurality of grid switches in multiple stages, waveform distortion compensating means for compensating for waveform distortion occurring in the communication path between arbitrary switch stages is provided in accordance with the signal speed. A high-speed communication path is obtained, characterized in that a plurality of such devices are provided on different paths, and means is provided for selecting a path including waveform distortion compensation means according to the signal speed when setting the path.

〔作用J 本発明は複数の格子スイッチを多段にリンク接続するこ
とによって構成される通話路において、リンク数の少な
い段間に波形歪補償回路を設けることにより、通話路の
出線に波形歪補償回路を設ける従来の高速通話路に比し
、大幅に波形歪補償回路の数を削減しようとするもので
ある。
[Operation J] The present invention provides waveform distortion compensation for the outgoing line of the communication path by providing a waveform distortion compensation circuit between the stages with a small number of links in a communication path constructed by linking a plurality of grid switches in multiple stages. Compared to conventional high-speed communication channels that are equipped with circuits, the number of waveform distortion compensation circuits is significantly reduced.

更に本発明は各径路毎に信号速度に応じた複数の波形歪
補償回路を設け、径路設定時に信号速度に応じた波形歪
補償回路を選択することによって、広範なビットレート
を有する種々のメディアの交換を可能にしようとするも
のである。
Furthermore, the present invention provides a plurality of waveform distortion compensation circuits according to the signal speed for each path, and selects the waveform distortion compensation circuit according to the signal speed when setting the path, thereby making it possible to use various media having a wide range of bit rates. It is intended to enable exchange.

更に本発明は信号速度に応じた複数の波形歪補償回路を
それぞれ互いに異なる径路に設け、径路設定時に信号速
度に応じた波形歪補償回路を含む径路を選択することに
よって、広範なビットレートを有する種々のメディアの
交換を可能にしようとするものである。
Furthermore, the present invention has a wide range of bit rates by providing a plurality of waveform distortion compensation circuits according to the signal speed on different paths, and selecting a path including the waveform distortion compensation circuit according to the signal speed when setting the path. It aims to enable the exchange of various media.

〔実施例〕〔Example〕

次にこの発明の実施例を図面を参照して説明する。第1
図は水弟1の発明の実施例を示すブロック図である。第
1図において第4図と同一番号を付したものは第4図と
同一の構成要素を示す。
Next, embodiments of the invention will be described with reference to the drawings. 1st
The figure is a block diagram showing an embodiment of Mizui's invention. In FIG. 1, the same numbers as in FIG. 4 indicate the same components as in FIG.

例えば加入者線交換機等においては、−次スイッチ40
2.二次スイッチ408をそれぞれ集線スイッチとして
使用し、入線数nkと出線数IN Sを等しく設計する
。このような場合には、スイッチ素子数の低減を図る為
に入線数nk、出線数mSに比し閉塞率が許される範囲
内で極力リンク数kt、stを少なく設計する。第1図
に示した水弟1の発明の実施例においては、波形歪補償
回路109.110,111.112を二次スイッチ4
05と三次スイッチ408との間に設けることにより第
4図に示した従来技術による高速通話路に比しくm5−
ts)個の波形歪補償回路の低減を図ったものである。
For example, in a subscriber line exchange, the -next switch 40
2. The secondary switches 408 are each used as a line concentration switch, and the number of incoming lines nk and the number of outgoing lines IN S are designed to be equal. In such a case, in order to reduce the number of switch elements, the number of links kt and st is designed to be as small as possible within the range that allows the blockage rate compared to the number of incoming lines nk and the number of outgoing lines mS. In the embodiment of Mizuo 1's invention shown in FIG.
05 and the tertiary switch 408, m5-
ts) waveform distortion compensation circuits.

第1図に示した入線413から出線419に到る径路に
着目すると、波形歪補償回路112は入線413と格子
スイッチ404の出線100との間で生じた波形歪の補
償を行なう、更に格子スイ・ソチ407の入線101と
出線419との間で生ずる波形歪に関しては、例えば波
形歪補償回路l12の出力部に予等化機能を付加するこ
とによって補償することができる。
Focusing on the path from the incoming line 413 to the outgoing line 419 shown in FIG. Waveform distortion occurring between the input line 101 and the output line 419 of the grid switch 407 can be compensated for, for example, by adding a pre-equalization function to the output section of the waveform distortion compensation circuit l12.

以上述べたように第1図に示した水弟1の発明の実施例
においては、大幅に波形歪補償回路の削減を図ることが
できる。
As described above, in the embodiment of the invention of Mizuhiro 1 shown in FIG. 1, it is possible to significantly reduce the number of waveform distortion compensation circuits.

第2図は水弟2の発明の実施例を示すブロック図である
。第2図によれば、波形歪補償回路の具体例は入力にそ
れぞれ波形歪が生じたディジタル信号が加えられた第1
の波形歪補償回路200゜第2の波形歪補償回路201
および第3の波形歪補償回路202と、前記3個の波形
歪補償回路200.201,202の出力のいずれか1
つを選択するスイッチ回路203とを含む。
FIG. 2 is a block diagram showing an embodiment of the invention of Mizui 2. According to FIG. 2, a specific example of the waveform distortion compensation circuit is a first circuit to which a digital signal with waveform distortion is applied to the input.
waveform distortion compensation circuit 200° second waveform distortion compensation circuit 201
and a third waveform distortion compensation circuit 202, and any one of the outputs of the three waveform distortion compensation circuits 200, 201, 202.
and a switch circuit 203 for selecting one.

第2図において波形歪補償回路200,201゜202
は例えば1.5 Mb/s 、  100Mb/ s 
In FIG. 2, waveform distortion compensation circuits 200, 201° 202
For example, 1.5 Mb/s, 100 Mb/s
.

800 M b / sのビットレートに対してそれぞ
れ最適に設計されており、通話路の径路設定時に、スイ
ッチ回路203によって高速ファクシーミリ信号の場合
には波形歪補償回路200を、通常の動画信号の場合に
番1波形歪補償回路201を、高精細動画信号の場合に
は波形歪補償回路202をそれぞれ選択出力する。
They are each optimally designed for a bit rate of 800 Mb/s, and when setting a communication path, a switch circuit 203 connects the waveform distortion compensation circuit 200 in the case of high-speed facsimile signals and the waveform distortion compensation circuit 200 in the case of normal video signals. In the case of a high-definition video signal, the waveform distortion compensation circuit 202 is selectively output.

このように第2図に示した波形歪補償回路を用いること
によって広範なピッI〜レートを有する種々の、メディ
アの交換を行なうことができる。
As described above, by using the waveform distortion compensation circuit shown in FIG. 2, it is possible to exchange various media having a wide range of pitch rates.

第3図は水弟3の発明の実施例を示すブロック図である
。第3図によれば水弟3の発明の実施例は300,30
1を含む複数の格子スイッチによって構成される一次ス
イッチ302と、303゜304を含む複数の格子スイ
ッチによって構成される二次スイッチ305と、306
,307を含む複数の格子スイッチによって構成される
三次スイッチと、二次スイッチの出線に設けられた30
9.310,311.312を含む複数の波形補償回路
とによって構成されている。
FIG. 3 is a block diagram showing an embodiment of the invention of Sui-Tei 3. According to Figure 3, the embodiment of Sui-Tei 3's invention is 300,30
A primary switch 302 constituted by a plurality of lattice switches including 303° 304;
, 307, and a tertiary switch composed of a plurality of lattice switches including lattice switches 307 and 30 provided on the output line of the secondary switch.
It is constituted by a plurality of waveform compensation circuits including 9.310, 311.312.

第3図に示した二次スイッチ305は更に321.32
2を含む複数の格子スイッチを有し、各格子スイッチの
出力には323.324,325゜326を含む複数の
波形歪補償回路が設けられている。
The secondary switch 305 shown in FIG.
The output of each grid switch is provided with a plurality of waveform distortion compensation circuits including 323, 324, 325° and 326.

第3図において一次スイッチ302と二次スイッチ30
5、二次スイッチ305と三次スイッチ308との間は
互いにそれぞれリンク接続されており、313,314
,315.316を含む複数の入線と、317,318
,319,320を含む複数の、出線との間を任意に接
続することができる。
In FIG. 3, the primary switch 302 and the secondary switch 30
5. The secondary switch 305 and the tertiary switch 308 are linked to each other, and 313, 314
, 315, 316, and 317, 318.
, 319, 320 can be arbitrarily connected to a plurality of outgoing lines.

ここで例えば波形歪補償回路309,310゜311.
312は100 M b 、/’ sのビットレートに
、波形歪補償回路323,324,325,326は8
00 M b 、−’ sのビットレートに対してそれ
ぞれ最適設計されている。
Here, for example, the waveform distortion compensation circuits 309, 310, 311.
312 has a bit rate of 100 Mb/'s, and waveform distortion compensation circuits 323, 324, 325, and 326 have a bit rate of 8
Optimal designs are made for bit rates of 00 M b and -' s, respectively.

第3図に示した本発明の第3の実施例においては、例え
ば入線313から出線319に到る径路を設定する際に
、通話信号速度が100 M b / sの場合には図
中破線で示した入線313−格子スイッチ30〇−格子
スイッチ304−波形歪補償回路312−格子スイッチ
307−出線319の径路を設定することによって波形
歪補償回路312を選択し、通話信号速度が800 M
 b / sの場合には図中実線で示した入線313−
格子スイッチ30〇−格子スイッチ322−波形歪補償
回路326−格子スイッチ307−出rL319の径路
を設定することによって波形歪補償回路326を選択す
る。
In the third embodiment of the present invention shown in FIG. 3, for example, when setting a route from an incoming line 313 to an outgoing line 319, if the call signal speed is 100 Mb/s, the broken line in the figure is set. The waveform distortion compensation circuit 312 is selected by setting the path of the input line 313 - grid switch 30 - grid switch 304 - waveform distortion compensation circuit 312 - grid switch 307 - output line 319 shown in .
In the case of b/s, the incoming line 313- shown as a solid line in the figure
The waveform distortion compensation circuit 326 is selected by setting the path of the grid switch 300 - the grid switch 322 - the waveform distortion compensation circuit 326 - the grid switch 307 - the output rL319.

このように第3図に示した水弟3の発明の実施例におい
ては、径路選択時に信号速度に応じた波形歪補償回路を
含む径路を選択することにより、広範なビットレートを
有する種々のメディアの交換を行なうことができる。
In this way, in the embodiment of Mizui's invention shown in FIG. 3, by selecting a path including a waveform distortion compensation circuit according to the signal speed at the time of path selection, it is possible to use various media having a wide range of bit rates. can be exchanged.

〔発明の効果〕〔Effect of the invention〕

以上述べたように、本発明によれば多くの波形歪補償回
路を必要とせず低消費電力、低価格の高速通話路を提供
することができる。
As described above, according to the present invention, a high-speed communication path with low power consumption and low cost can be provided without requiring many waveform distortion compensation circuits.

更にまた本発明によれば広範なビットレートを有する種
々のメディアを交換することのできる高速通話路が得ら
れる。
Furthermore, the present invention provides a high speed communication path capable of exchanging a variety of media having a wide range of bit rates.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は水弟1の発明の実施例を示すブロック図、第2
図は水弟2の発明の実施例を示す図であり、波形歪補償
回路の具体例を示す図、第3図は本革3の発明の実施例
を示す図、第4図は従来技術による高速通話路の一例を
示すブロック図、第5図は第4図中の波形歪補償回路の
第1の具体例を示すブロック図、第6図は第4図中の波
形歪補償回路の第2の具体例を示すブロック図である。 300.301,303.304,306,307.3
21,322,400,401,403゜404 、4
06 、407・・・格子スイッチ、109゜110.
111,112,309,310,311.312,3
23,324,325,326゜409.410,41
1.412・・・波形歪補償回路。 第 5  図 第 t 凹
Figure 1 is a block diagram showing an embodiment of Mizui's invention.
The figure is a diagram showing an embodiment of the invention of Mizui 2, and a diagram showing a specific example of a waveform distortion compensation circuit, Figure 3 is a diagram showing an embodiment of the invention of Genhaku 3, and Figure 4 is a diagram based on the prior art. FIG. 5 is a block diagram showing an example of a high-speed communication path, FIG. 5 is a block diagram showing a first specific example of the waveform distortion compensation circuit in FIG. 4, and FIG. 6 is a block diagram showing a second example of the waveform distortion compensation circuit in FIG. It is a block diagram showing a specific example. 300.301, 303.304, 306, 307.3
21,322,400,401,403°404,4
06, 407... Lattice switch, 109°110.
111,112,309,310,311.312,3
23,324,325,326゜409.410,41
1.412... Waveform distortion compensation circuit. Fig. 5 t concave

Claims (1)

【特許請求の範囲】 1、複数の格子スイッチを多段に接続して構成される通
話路において、任意のスイッチ段間に前記通話路におい
て生ずる波形歪を補償する波形歪補償手段を備えること
を特徴とする高速通話路。 2、複数の格子スイッチを多段に接続して構成される通
話路において、任意のスイッチ段間に前記通話路におい
て生ずる波形歪を補償する波形歪補償手段を信号速度に
応じて複数個設け、径路設定時に前記信号速度に応じた
波形歪補償手段を選択する手段を備えることを特徴とす
る高速通話路。 3、複数の格子スイッチを多段に接続して構成される通
話路において、任意のスイッチ段間に前記通話路におい
て生ずる波形歪を補償する波形歪補償手段を信号速度に
応じてそれぞれ互いに異なる径路に複数個設け、径路設
定時に前記信号速度に応じた波形歪補償手段を含む径路
を選択する手段を備えることを特徴とする高速通話路。
[Scope of Claims] 1. In a communication path configured by connecting a plurality of grid switches in multiple stages, a waveform distortion compensating means is provided between arbitrary switch stages to compensate for waveform distortion occurring in the communication path. A high-speed communication route. 2. In a communication path configured by connecting a plurality of grid switches in multiple stages, a plurality of waveform distortion compensating means for compensating for waveform distortion occurring in the communication path between arbitrary switch stages is provided according to the signal speed, and the path is A high-speed communication path characterized by comprising means for selecting a waveform distortion compensation means according to the signal speed at the time of setting. 3. In a communication path configured by connecting a plurality of grid switches in multiple stages, waveform distortion compensating means for compensating for waveform distortion occurring in the communication path between arbitrary switch stages is placed on different paths depending on the signal speed. A high-speed communication path, characterized in that it is provided with a plurality of means for selecting a path including a waveform distortion compensating means according to the signal speed when setting the path.
JP26433885A 1985-11-22 1985-11-22 High speed channel Pending JPS62123889A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26433885A JPS62123889A (en) 1985-11-22 1985-11-22 High speed channel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26433885A JPS62123889A (en) 1985-11-22 1985-11-22 High speed channel

Publications (1)

Publication Number Publication Date
JPS62123889A true JPS62123889A (en) 1987-06-05

Family

ID=17401782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26433885A Pending JPS62123889A (en) 1985-11-22 1985-11-22 High speed channel

Country Status (1)

Country Link
JP (1) JPS62123889A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04124728U (en) * 1991-04-30 1992-11-13 テイーオーエー株式会社 switch device
US6959003B1 (en) 1998-09-22 2005-10-25 Kabushiki Kaisha Toshiba Serial transmission path switching system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04124728U (en) * 1991-04-30 1992-11-13 テイーオーエー株式会社 switch device
US6959003B1 (en) 1998-09-22 2005-10-25 Kabushiki Kaisha Toshiba Serial transmission path switching system

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