JPS62123826A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To stabilize the threshold characteristic of a MOS transistor (TR) by applying a power voltage of the pre-stage of a back gate of a CMOS TR receiving an output of the circuit of pre-stage different in power voltage. CONSTITUTION:The operating power voltage of the pre-stage circuit is applied to a linear circuit section 2 having a larger operating power voltage than that of the CMOS circuit 1 and a back gate of a CMOS TR M1 of an interface circuit section 3 interfacing with the CMOS circuit 1. Thus, the production of the polarization of the residual component is prevented to a gate insulation film of a MOS TR and the threshold characteristic of the MOS TR is made stable to stabilize the input operation.

Description

[Detailed Description of the Invention] [Technical Field] The present invention is particularly effective when applied to semiconductor integrated circuit device technology and to a semiconductor integrated circuit device in which two types of circuit sections that operate at different power supply voltages are formed together. technology, such as CM that operates with relatively low power supply voltage.
The present invention relates to a technique that is effective when used in an analog/digital mixed semiconductor integrated circuit device in which an OS digital circuit section and a linear circuit section that operates at a relatively high power supply voltage are formed together.

[Background technology]

For example, a bipolar 970MO8 coexisting semiconductor integrated circuit device, as introduced in Nikkei McGraw-Hill, Inc., "Nikkei Electronics October 12, 1981 issue, 275," page 111, is a so-called analog/digital mixed semiconductor integrated circuit device. As a device, it should be possible to handle both analog and digital signals within one semiconductor integrated circuit device.

FIG. 3 shows an outline of a mixed analog/digital semiconductor integrated circuit device previously studied by the present inventors. A digital circuit section 1 and an IJ near circuit section 2 are formed together in a semiconductor integrated circuit device 100 shown in the figure.

At the same time, part of the output of the linear circuit section 2 is input to the digital section 1.

In this case, the digital circuit section 1 connects mutually complementary pairs.
It is constructed using channel MOS transistors M1 to Mm and n-channel MOS transistors M2 to Mn, and is operated by a predetermined power supply voltage Vdd-GND (about 5V). Furthermore, the linear circuit section 2 is constructed using bipolar transistors, etc., and is connected to the power supply voltage Vdd-GND (approximately 5 V).
voltage Vcc-GND (e.g. about 12V
).

However, in the above-mentioned analog/digital mixed type semiconductor integrated circuit device 100, the operating power supply voltages Vdd and VCC of the digital circuit section 1 and the linear circuit section 2 are large (different, which causes the following problems. The present inventors have clarified that the occurrence of JP.

That is, in the semiconductor integrated circuit device 100 shown in FIG. 3, the power supply voltage Vdd (approx. A voltage close to the power supply voltage Vcc (approximately 12 V) on the linear circuit section 2 side, which is also high, may be applied.

Then, as shown in FIG. 4, a large reverse bias voltage (Vcc - Vdd - about 7V) is applied to the gate electrode 14 of the p-channel MOS transistor M1. When this reverse bias voltage (Vcc - Vdd) is applied, residual ion polarization occurs in the thickness direction of the gate insulating film 17a. When this ion polarization occurs, the threshold value of the MOS transistor M1 changes, making it difficult to turn it on. That is, 0MO8) transistor M1. The inventors of the present invention have revealed that a problem arises in that the first input stage using M2 does not operate properly.

In addition, in FIG. 4, 10 is an n-type semiconductor layer,
It becomes the back gate of p-channel MOS transistor M1. 12 indicates a p+ type drain/source diffusion layer.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit device technique in which the input operation of a MOS transistor receiving an output from a circuit section having a relatively high operating power supply voltage is always performed stably and normally.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief description of typical inventions disclosed in Book 11 is as follows.

In other words, a digital circuit section consisting of a CMO3) transistor formed using a complementary pair of jp channel MOS transistors and an n channel MOS transistor, together with a second circuit section operating at a relatively high power supply voltage. In the formed semiconductor integrated circuit device, the operating power supply voltage of the second circuit section is applied to the back gate of the CMOS transistor constituting the first input stage of the digital circuit section, so that the MO8) gate insulating film of the transistor is The purpose is to prevent residual polarization from occurring in the MOS transistor, thereby stabilizing the threshold characteristics of the MOS transistor, and thereby ensuring that the input operation of the digital circuit section is always performed stably and normally. It is something to be achieved.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a semiconductor integrated circuit device to which the technology according to the present invention is applied.

The semiconductor integrated circuit device [1i100 shown in the figure is a so-called analog/digital mixed type semiconductor integrated circuit device, in which two types of circuit sections, a first circuit section 1 and a second circuit section 202, are formed together. There is. In this case, a digital circuit section 1 is formed as the first circuit section 1, and a linear circuit section 2 is formed as the second circuit section. The 1y near circuit section 2 includes transistor Q++ and resistor R, .
The emitter output of the output circuit composed of R is input to the digital section 1 via the interface circuit section 3.

Further, the digital circuit section 1 is configured using jp channel MO8) transistors M3 to Mm and n channel MOS transistors M4 to Mn, which are complementary pairs to each other, and is operated by a relatively low power supply voltage Vdd-GND (approximately 5 V). Let me make you do it.

ing. In addition, the linear circuit section 2 is configured using bipolar transistors, etc., and has a relatively high power supply voltage V.
It is designed to be operated by cc-GND (approximately 12v).

Here, the semiconductor integrated circuit device 1 of the embodiment shown in FIG.
00, in addition to the above-described configuration, the operating power supply voltage Vcc of the second circuit section is applied to the back gates of the CMOS transistors M1 and M2 of the interface circuit section 3. Specifically, the source is at the power supply voltage V
p-channel MO8) transistor M1 connected to dd
The back gate of is connected to the high power supply voltage VCC side. As a result, the p-channel MOS transistor M
Even if the high power supply voltage Vcc of the linear circuit section 2 is applied to the gate of the back gate 1, the gate voltage (Vcc - Vdd) relative to the back gate is kept at a potential that does not cause the ion polarization. It starts to sag. As a result, the threshold characteristic of the MOS transistor M1 is stabilized, and the input operation of the digital circuit section 1 can always be performed stably and normally. In addition, the MO used in the digital circuit section 1
The drains and back gates of the S transistors M3 to Mm and M4 to Mn are commonly connected.

FIG. 2 shows the output stage of the linear circuit section 2 including a transistor Q and an interface circuit section 30M0S transistor M1. The cross-sectional states of M2 and the transistors M3 and M4 at the first input stage of the digital circuit section 10 are shown.

As shown in the figure, the interface circuit section 3 is
8) The transistors Ml and M2 are n-type transistors on the p-type semiconductor substrate 9.
type semiconductor region 10 .

In this case, the p-channel MO transistor M1 is formed in the n-type semiconductor region 10. And this n-type layer 1
0 is connected to the high voltage power supply Vcc side as the back gate of the p-channel 1L/MOS transistor M1.

In FIG. 2, p-channel MO8) transistor Ml
, M3 includes a p medium type drain/source diffusion layer 12, an n+ type scattering layer 13 for back gate connection, a gate electrode 14,
A gate insulating film 17a and the like are formed. In addition, the n-channel MO8) transistors M2 and M4 are formed in the p-type well diffusion layer 11, and further include an n-medium drain/source diffusion layer 15, a p+-type scattering layer 16 for back gate connection, a gate electrode 14, and a gate electrode 14. It is composed of an insulating film 17a and the like. In addition, 17 indicates a surface oxide film, and 18 indicates an electrode made of aluminum or the like. Furthermore, the bipolar transistor Q has an emitter layer 20. It is composed of a base layer 21 , an n medium-sized buried layer 22 , and an n medium-sized collector electrode extraction layer 23 .

A further feature is that the MO of the interface circuit section 3
S) The transistors M1 and M2 are electrically separated from the digital circuit section 1 by the p++ layer 19, so that a high potential can be applied as the back gate of the p-channel MO8MI of the interface circuit section 3. . This p
Since the ++ layer 19 can be formed at the same time as the p++ layer 19 for isolating the bipolar transistor Q, there is no additional process.

On the other hand, the digital circuit section 1 does not have the p+ type circuit 19, so that high integration can be achieved.

〔effect〕

(1) A CMO constructed using a mutually complementary pair of p-channel MOS transistors and n-channel MO8) transistors. Together with the digital circuit section using transistors, there is a second circuit section that operates at a relatively high power supply voltage. In a semiconductor integrated circuit device formed in a semiconductor integrated circuit device, the gate insulation of the MO8) transistor is applied to the bank gate of the MO8) transistor at the first stage of the input stage of the digital circuit. It is now possible to prevent residual polarization from occurring in the film, thereby stabilizing the threshold characteristics of the MOS transistor and ensuring that the input operation of the digital circuit section is always stable and normal. This has the effect of making it easier to use.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples (although it is possible to make various changes without departing from the gist of the invention). For example, the logic circuit in the digital circuit section 1 is a Bi-C transistor in which a MOS transistor and a bipolar transistor are combined in the logic circuit.
It may also be an MO8 type circuit.

[Application field]

The invention made by the present inventor has been explained above in the case where it is applied to the technology of analog/digital mixed type semiconductor integrated circuit devices, which is the field of application that forms the background of the invention.
The present invention is not limited thereto, and can be applied to, for example, pure MO8W semiconductor integrated circuit device technology or digital-only semiconductor integrated circuit device technology.

[Brief explanation of drawings]

1 is a circuit diagram showing an embodiment of a semiconductor integrated circuit device to which the present invention is applied; FIG. 2 is a sectional view showing the state of a semiconductor structure in a part of the circuit shown in FIG. 1; FIG. 4 is a circuit diagram showing the configuration of a semiconductor integrated circuit device studied prior to the present invention, and FIG. 4 is an equivalent circuit diagram showing the state of elements in a part of the circuit shown in FIG. 1... Digital circuit section as a first circuit section, 2...
・IJ as a second circuit section Near circuit section, 3... Interface circuit section, Vdd... Operating power supply voltage on the digital circuit section 1 side, VCC... Operating power supply voltage on the linear circuit section 2 side, 10... N-type layer serving as a back gate of a p-channel MOS transistor. 7'-・,

Claims (1)

[Claims] 1. A first circuit section configured using a p-channel MOS transistor and an n-channel MOS transistor forming a complementary pair, and a power supply voltage higher than the operating power supply voltage of the first circuit section. A semiconductor integrated circuit device is formed together with a second circuit section that is operated in a semiconductor integrated circuit device, and an output of the second circuit section is inputted to the first circuit section.
1. A semiconductor integrated circuit device characterized in that an operating power supply voltage of a second circuit section is applied to a back gate of a CMOS transistor receiving an output of the second circuit section. 2. The semiconductor integrated circuit device according to claim 1, wherein a digital circuit is formed in the first circuit section, and a linear circuit is formed in the second circuit section.