JPS62123766A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To control the threshold voltage of a pass transistor to be the optimum value and simplify the manufacturing process of high concentration P<+> type region by a method wherein a P<+> type layer is formed on a P<-> type substrate and higher concentration P<+> type regions are selectively formed. CONSTITUTION:On a P<-> type substrate 1, a P-type epitaxial layer 14, which has a higher impurity concentration than the substrate 1, is formed by epitaxial growth. Then, after a mask is formed on the channel region of a pass transistor, a P-type impurity is implanted and higher concentration P<+> type regions 15 and 16 are formed. Then the 2nd layer gate electrode 17 is formed and an N<+> type impurity is implanted by a self-alignment process by using the electrode 17 as a mask to form a charge storing region 6 and a bit wire 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory that uses the presence or absence of electric charge as stored information.

[Conventional technology]

FIG. 2 is a sectional view showing a conventional semiconductor memory disclosed in, for example, Japanese Patent Application Laid-Open No. 57-210665.

In the figure, (1) is a semiconductor substrate with P-type tetraelectricity,
(2) and <<3>> are gate electrodes of the first and second layers, (4) is a gate insulating film, (C) is an interlayer insulating film, (6)
is the N"1 region as a charge storage region, (7) is a relay region as a bit line, (8) is an isolation insulating film for isolation between elements, and (9) is a P+ region for isolation between elements. and
The first layer gate electrode (2) is connected to the power supply, the second layer gate electrode (3) is connected to the word line, and each N region (6), (7) and the substrate (1) are connected to each other. In between, there is a depletion layer αG.

0η is formed.

Furthermore, a furnace region (6) as the charge storage region.

A P+ region having a higher concentration than the substrate (1) is implanted and diffused so as to commonly surround a furnace region (7) serving as a bit line. Is it possible to selectively implant and diffuse P+ impurities into the P- type semiconductor substrate (1) to prevent inversion and parasitism? After forming the region (9) and the element isolation insulating film (8) at the same time, a P+ region (to) as an operating region is formed by implanting and diffusing P+ impurities using the insulating film (8) as a base. , and then the normal forming procedure? region (6), gate electrode (2LN” region (7)
, gate electrode (3), etc., but what about both r regions (6) and (7)? It will be surrounded by the realm.

Further, the Vanu transistor in this conventional example is formed in a P+ region (total) having a higher concentration than the substrate. Normally, the threshold voltage of the bus transistor is set higher than the threshold voltage of the peripheral transistors in consideration of stable operation of the memory, but if the threshold voltage is too high for the concentration of region a3, then the N+ After the formation of the regions 6), (7), it is possible to control the threshold voltage of the bus transistor by means of the channel dose of the furnace.

Note that the wiring portion and protective film are omitted here.

Further, to simplify the explanation, the region (6) is defined as a diffusion-resistant region, but in the case of a normal configuration, the gate insulating film (4
) by applying a positive potential to the first layer gate electrode (2), an inversion layer of r is induced in a portion of the semiconductor surface corresponding to the region (6), and charges are accumulated.

In the conventional configuration, the state where electrons are accumulated in the N+ region 6) as the charge accumulation region of the memory cell is set to "0", and the state where no electrons are stored is set to "1".Then, the bit line The potential of the dynamic region (7) is precharged to a predetermined potential by the action of a sense amplifier (not shown).

Here, the potential of the word line rises, and when the potential of the second layer gate voltage i (3) as a transfer gate connected to this word line becomes higher than the threshold voltage, this gate is turned into a pole (3). A channel of the N+ inversion layer is formed directly under the N'' regions (6) and (7), thereby providing conduction between the two N'' regions (6) and (7).

Therefore, if the storage information of the memory cell is currently "O", that is, electrons are accumulated in the N+ area 6), this furnace area (6) and the N+ area 7) serving as the bit line
As a result, the potential of this N+ region 7), which had been held at the pre-charge potential, decreases, and conversely, the stored information of the memory cell becomes "1", that is, electrons are transferred to the N+ region 6). In the case of no accumulation, this conduction causes the potential of the N+ region 7), which was at an intermediate potential, to rise. A sense amplifier (not shown) senses and extracts the change in the potential of the pin M, and at the same time, the same stored information is refreshed and written into the memory cell again within the same cycle.

On the other hand, among the electron-hole pairs generated when radiation such as alpha rays enters the memory chip, electrons are collected in these charge storage regions and bit lines, causing malfunctions that reverse the original stored information ( 16kDRAM (hereinafter referred to as soft error)
It has become noticeable since then.

Soft errors occur when electrons and holes are generated when radiation such as alpha rays enters the chip, and the electrons are collected in the N+a region (6) + (7), which acts as a charge accumulation region or bit line. caused by being caused. In other words, before the α rays entering the chip lose energy and stop, they generate many electron-hole pairs along their range, forming a depletion layer αG, (
The electron-hole pairs generated in b) are immediately separated by the electric field inside the depletion layer, and the electrons are separated from the N+ region 6), (
7), the holes flow down through the substrate (1). In addition, the electron/hole pairs generated inside the N+ regions 6) and (7) do not contribute to the increase or decrease of electrons at all because they recombine, and the electrons/hole pairs generated inside the substrate (1) do not contribute to the increase or decrease of electrons at all. For hole pairs, only the electrons that have reached the depletion layer aa + aυ by diffusion are collected in the N+ region 6) 3 (7), causing a soft error, and the others are recombined in the substrate (1). It turns out.

Therefore, in this example, each N region (6),
(7) and the depletion layer (10
, the width of αυ becomes smaller and each N+ region 6) l (7
) becomes larger, and secondly, each N+ region 6) ,
(7) is formed in the P+ region (to), so the electrons diffused from the P- type substrate (1) are recombined within the P+ region and reach each region (a) + (7). 8th, P
Since a potential barrier against electrons is formed at the interface between the − type substrate (1) and the P+ region 4, electrons with low energy diffused from the P− substrate (1) are not allowed to pass through. And each area (a) by the first point
, (7) The difference in the number of electrons corresponding to "O" and "1" accumulated in the second and Each furnace head area (6) by the eighth point.

(7) It is possible to prevent electrons from diffusing into K, thereby eliminating the occurrence of soft errors.

[Problem that the invention seeks to solve]

Since the conventional semiconductor memory is constructed as described above, it takes a long time in the manufacturing process to form the P+ region with a higher concentration than the substrate (1), and it is difficult to control the concentration. There were problems such as the threshold voltage and junction breakdown voltage of the pass transistor being easily fluctuated.

This invention was made to solve the above-mentioned problems, and it not only shortens the time required for the manufacturing process, but also makes it easy to control the concentration of a layer that has the same conductivity type as the semiconductor substrate and has a higher concentration than that of the semiconductor substrate. The purpose of this invention is to obtain a semiconductor memory in which the threshold voltage and junction breakdown voltage of pass transistors can be easily controlled.

[Means for solving problems]

The semiconductor memory according to the present invention employs a wafer in which an epitaxial layer of a first conductivity type is grown on a semiconductor substrate of a first conductivity type, and a channel of a pass transistor formed on this wafer is used. By masking the region and implanting impurities of the same conductivity type into the epitaxial layer to form a highly concentrated P+ region, memory cells with pass transistors and MIS capacitors are formed on the surface of this wafer.

[Effect]

The epitaxial layer in this invention simplifies the manufacturing process, makes it easy to control its own concentration, and makes it easy to control the threshold voltage and junction breakdown voltage of the pass transistor. In addition, implanting the same 4' type impurity into the epitaxial layer and providing a highly concentrated P+ region reduces the size of the depletion layer between the bit line and the impurity layer forming the memory cell, and reduces the size of the depletion layer in the P- substrate. It forms a potential barrier to electron injection from t- and provides abundant recombination centers for the injected electrons.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, the same numbers as in the conventional example of FIG. 2 indicate the same or corresponding parts. α◆ is a P layer epitaxially grown on a P− substrate (1). This epitaxial wafer is manufactured by the manufacturing process shown in FIG. Third
In fa) of the figure, the steps from field region formation to formation are the same as in the conventional example. Next, using a mask material QI (resist or the like), an impurity of the same conductivity type as that of the Evitakinya μ layer is implanted to form an even higher concentration region (c) Ql. Next, as shown in Figure fb), a second layer gate electrode αη is provided, and using this as a mask, N+ is implanted in a self-line process to form (e) (7).

Furthermore, as shown in Figure C1, a first layer of gate electrodes is formed.The subsequent steps are manufactured by the same manufacturing process as in the conventional example.

Since the concentration of the epitaxy tough 22 layer α4 can be easily controlled arbitrarily, it is easy to set the threshold voltage of the pass transistor controlled by the word line to an optimum value.

Also, the N+ layer (6) that forms memory cells and bit lines (
The thickness of the depletion layer αGQI) between 7) and the more highly concentrated P+ region αυQe implanted with impurities of the same conductivity type in the epitaxy tough 22 layer a4 can be narrowly controlled, and the electrons induced by α rays in this layer can be controlled narrowly. - It is possible to reduce the number of hole pairs to the level of a soft error that does not pose a practical problem. Also, the engineered bitaxial layer α as a lifetime killer
The effect of the potential barrier between the P layer αQαQ-P layer Q41-P layer (1) is also the same as in the conventional example. Since the epitaxial P layer is employed, the impurity implantation/diffusion process required to form the highly concentrated P+ region 05 (14G) is easier than that for forming the P+ region shown in FIG.

According to experiments, the impurity concentration of the P layer (1) is 10"m, and the impurity concentration of the P layer α4 is 10"-10.
16cIrL"P" layer Qf9 QQ impurity concentration 1
016~10"Cm-', [ of N+ layer (6) (7)
It was found that approximately 1018 to 10'' (1771) has a sufficient improvement effect on soft errors and at the same time has sufficient margin for junction breakdown voltage.

The threshold voltage of the pass transistor controlled by the word line can also be controlled to an optimum value.

Alternatively, the epitaxy/I/P+ layer α4 may not be formed over the entire surface of the wafer, but may be selectively grown only on the array portion of the memory cell μ.

Furthermore, although the above embodiment is applied to a dynamic type, it can also be applied to a static type as well.
This can also be applied when the N channel is the P channel.

〔Effect of the invention〕

As described above, according to the present invention, a memory element is formed on a wafer formed by epitaxially growing a first conductivity type layer having a higher concentration than that of the first conductivity type semiconductor substrate,
A region with a higher concentration than the epitaxial layer is provided in a region other than the channel region of the pass transistor of the word line, and a layer of the second conductivity type that becomes the bit line and capacitor region of the memory cell is formed on the surface of the high concentration region. , a significant improvement in the soft error rate due to α rays can be expected, the manufacturing process for the P+ concentration can be simplified, and the threshold value controller μ of the pass transistor can be easily set to an optimal value.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a semiconductor memory according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional semiconductor memory. Fig. 8 is a manufacturing process diagram of Fig. 1 (1)...semiconductor substrate, Q4)...epitaxial layer, (6)...charge storage region, (7)...1 same as bit diagram Codes indicate the same or corresponding parts.

Claims (4)

[Claims] (1) epitaxially growing a layer of a first conductivity type on a semiconductor substrate of a first conductivity type, the concentration of which is higher than that of the substrate;
A region of the same first conductivity type and having a higher concentration than the epitaxial layer is formed thereon, and regions of the second conductivity type as a charge storage region and a bit line, respectively, and first and second conductivity type regions are formed thereon. A semiconductor memory characterized in that a second gate electrode is formed. (2) The semiconductor memory according to claim 1, wherein the channel region of the second gate electrode, which is a word line, is made of the epitaxial layer of the first conductivity type. (3) The impurity concentration of the epitaxial layer is 10^1^5~
10^1^6cm^-^3 The impurity concentration of the first conductivity type region, which is higher than the above-mentioned epitaxial layer, is 10^
1^6 to 10^1^8 cm^-^3, and the impurity concentration of the second conductivity type region is 10^1^8 to 10^2^0. term or second
Semiconductor memory described in Section 1. (4) The semiconductor memory according to any one of claims 1 to 3, wherein the first conductivity type region having a higher concentration than the epitaxial layer is formed by ion implantation.