JPS62122404A - Differential amplifier - Google Patents

Abstract

PURPOSE:To drive the titled amplifier by a high frequency signal by connecting a gate of the 1st load MIS transistor (TR) and a gate of the 2nd load MIS TR to a fixed voltage source causing a voltage difference larger than the voltage difference between a source and a drain. CONSTITUTION:The gates of the load P-channel MISFETs Q1, Q2 are connected to a negative power supply Vss1. Since the gate-source voltage is larger than that connected to the drain, the capability is improved and the gate width to obtain the same load resistance is decreased, then the drain junction capacitance is reduced and the gate capacitance of the MISFETs Q1, Q3 is decreased because the gate width is reduced and the dividing ratio of the gate capacitance to the drain side is reduced less than the division to the source, and the frequency keeping the gain as the unity is increased. Thus, the high frequency drive is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a differential amplifier, and particularly to a differential amplifier that can be driven at a high frequency.

[Conventional technology]

Conventionally, a differential amplifier in a complementary MIS integrated circuit has been configured as shown in FIG. Qta+Qa.

are P-channel MISFRT, Qa*, Q□, Q3.
is N-channel MISFET, VINl, Vl* are differential inputs, Vo8 is constant bias input, Vcc, , Vs
s is a power supply, and Vo, is an output.

The gate electrodes of the load P-channel MI8FETs are connected to their respective drain electrodes and outputs.

In such a differential amplifier, the differential input Vnr.

Since there is a difference in the channel conductance of MISFET29.31 based on the voltage difference between VIN and
A difference occurs between the currents passing through the FETs 29 and 31, and this current difference is output as a voltage difference amplified by the presence of the MISFETs 28 and 30.

[Problem to be solved by the invention]

However, in a conventional differential amplifier, ■ drain junction capacitance of P-channel and N-channel MISFET @ gate capacitance divided on the source side of P-channel MISFET ■ gate divided between source and drain side of N-channel MISFET The capacitor acts as a load in addition to the external load connected to the output, and the frequency at which the gain is 1 times cannot be increased to about 5QQMHz or higher, and high-speed operation is not possible.
Since the gates of ET28.30 were connected to their respective drains, the output voltage was (supply voltage Vcc,) −(
When the threshold value of MISFBT Qu, Q, , is exceeded, the load MI 8 FBT Qu, Qs. However, there was a problem in that the amplitude of the output voltage could not be increased above a certain level.

[Means for solving the problem] The present invention provides a set of a first load MIS transistor and a first amplification MIS transistor connected in series, a second load MIS transistor and a second amplification MIS transistor connected in series. A pair of M/S transistors are placed in parallel between a high voltage source and a low voltage source, and an input signal is applied to the gate of the first amplification MID transistor and the second amplification MIS transistor, respectively. In a differential amplifier that obtains an amplified output at each drain, a voltage difference between the gate of the first load MID transistor and the gate of the second load MIS transistor is greater than the voltage difference between the source and drain. The gist is that it is connected to a fixed voltage source generated between

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. Q,, Q,, Q
,.

are P-channel MISFETs, Qt, Q4. Qll
, Qy is an N-channel MIsFET, VIN,, V
IN, is input, Vol, Vo is output, Vssl is negative power supply, Vcc is positive power supply, differential input VIN, -V
This is a differential amplifier that outputs differential outputs Vo and -Vo with respect to IN. Load P-channel MISFB
The gates of TQ+ and Qs are connected to the negative power supply V88. It is connected to the. Therefore, the voltage between the gate and the lease becomes larger than when connected to the drain, so the capacity is improved, and the gate width becomes smaller to obtain the same load resistance value, so the drain junction capacitance can be reduced. As for the gate capacitance of Q, the above-mentioned gate width can be made small, and also K.

Since the division of the gate capacitance toward the drain side is smaller than the division toward the source side, K can still be made smaller. Therefore, since the load capacitance is smaller than that of the conventional complementary MI8 differential amplifier, the frequency at which the gain is 1 times can be increased.

In addition, in the conventional complementary MI8 differential amplifier, the load P
Since the gate electrode of the channel MISFET is connected to its drain, the output is Vcc, -1■π1(VTP
:Threshold voltage of P-channel MISFBT for load), but in this embodiment, the gate electrode is connected to the negative power supply Vs.
Since s and 4C are connected, the output swings at Vcclj.

FIG. 2 also shows an embodiment of the present invention. This is P of Q8-Q1
Since the gate electrodes of q to q1 are grounded in the data flip-flop whose load is the channel MISFET,
For the same reason as the embodiment shown in FIG. 1, it operates faster than the conventional one, and the output swings up to the power supply voltage DD and has a large amplitude.

〔effect〕

As explained above, according to the present invention, the load M
Since a voltage that generates a voltage difference between the source and gate that is larger than the voltage between the source and drain is applied to the gate of the IS transistor, the gate size of the load MIS transistor can be reduced, and as a result, the differential amplifier Since the parasitic capacitance added to the sum of outputs can be reduced, the effect of enabling high frequency driving is obtained.

In addition, since the voltage difference between the gate and source of the load MI8 transistor is large, the output amplitude of the differential amplifier can also be increased.

[Brief explanation of drawings]

FIG. 1 is an electrical circuit diagram of one embodiment of the present invention, FIG. 2 is an electrical circuit diagram of another embodiment, and FIG. 3 is an electrical circuit diagram of a conventional example. Q,, Q,, Q, to Qll...M for load
IS transistor, Q,, Q,, Q,, Q□・
...M engineering S transistor for amplification, ■881...
...Fixed voltage source. Agent: Susumu Uchihara, patent attorney. Vss diagram 3

Claims (1)

[Claims] A set of a first load MIS transistor and a first amplification MIS transistor connected in series, and a second
A set of a load MIS transistor and a second amplification MIS transistor is arranged in parallel between a high voltage source and a low voltage source, and the gate of the first amplification MIS transistor and the gate of the second amplification MIS transistor are arranged in parallel between a high voltage source and a low voltage source. In a differential amplifier that applies an input signal to each drain and obtains an amplified output to each drain, the gate of the first load MIS transistor and the gate of the second load MIS transistor are connected to a voltage greater than the voltage difference between the source and drain. A differential amplifier characterized in that it is connected to a fixed voltage source that produces a difference between the gate and the source.