JPS62121834U - - Google Patents
Info
- Publication number
- JPS62121834U JPS62121834U JP793686U JP793686U JPS62121834U JP S62121834 U JPS62121834 U JP S62121834U JP 793686 U JP793686 U JP 793686U JP 793686 U JP793686 U JP 793686U JP S62121834 U JPS62121834 U JP S62121834U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- capacitor
- grounded
- gate circuit
- whose
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Pulse Circuits (AREA)
Description
第１図は本考案の一実施例の回路図、第２図、
第３図は従来のパルス幅調整回路の回路図である
。
１……ＥＣＲのＯＲ，ＮＯＲゲート回路、ＶＲ
１……可変抵抗器、Ｒ１，Ｒ２，Ｒ３……抵抗、
Ｃ１，Ｃ２……コンデンサ、Ｖ１……入力信号電
圧、Ｖ２，Ｖ３……出力信号電圧、−Ｖｃｃ……
電源電圧、Ｄ１……ダイオード。
Figure 1 is a circuit diagram of an embodiment of the present invention; Figure 2 is a circuit diagram of an embodiment of the present invention;
FIG. 3 is a circuit diagram of a conventional pulse width adjustment circuit. 1...ECR OR, NOR gate circuit, VR
1...Variable resistor, R1, R2, R3...Resistance,
C1, C2... Capacitor, V1... Input signal voltage, V2, V3... Output signal voltage, -Vcc...
Power supply voltage, D1...diode.
Claims (1)
と、前記第一のコンデンサの他端に一端を接続す
る第一の抵抗の他端に入力を接続するＯＲ，ＮＯ
Ｒゲート回路と、前記第１の抵抗の他端に一端を
接続する第二の抵抗と、前記第二の抵抗の他端に
一端を接続する第三の抵抗と、前記第二の抵抗の
他端に一端を接続し他端を接地する第二のコンデ
ンサと、前記第三の抵抗の他端にしゆう動端子を
接続し一端を接地し他端を前記ＯＲ，ＮＯＲゲー
ト回路の出力に接続した可変抵抗器とを具備する
ことを特徴とするバルス幅調整回路。 A first capacitor to which an input signal is applied at one end, and an OR, NO whose input is connected to the other end of a first resistor whose one end is connected to the other end of the first capacitor.
an R gate circuit; a second resistor having one end connected to the other end of the first resistor; a third resistor having one end connected to the other end of the second resistor; A second capacitor is connected to one end and the other end is grounded, and a sliding terminal is connected to the other end of the third resistor, one end is grounded and the other end is connected to the output of the OR/NOR gate circuit. A pulse width adjustment circuit comprising a variable resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP793686U JPS62121834U (en) | 1986-01-22 | 1986-01-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP793686U JPS62121834U (en) | 1986-01-22 | 1986-01-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62121834U true JPS62121834U (en) | 1987-08-03 |
Family
ID=30791854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP793686U Pending JPS62121834U (en) | 1986-01-22 | 1986-01-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62121834U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6051295A (en) * | 1983-08-26 | 1985-03-22 | 南野建設株式会社 | Internal pushing construction method of pipe body |
| JPS60235519A (en) * | 1984-05-08 | 1985-11-22 | Nec Corp | Self-bias gate circuit |
-
1986
- 1986-01-22 JP JP793686U patent/JPS62121834U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6051295A (en) * | 1983-08-26 | 1985-03-22 | 南野建設株式会社 | Internal pushing construction method of pipe body |
| JPS60235519A (en) * | 1984-05-08 | 1985-11-22 | Nec Corp | Self-bias gate circuit |