JPS62121574U - - Google Patents
Info
- Publication number
- JPS62121574U JPS62121574U JP845686U JP845686U JPS62121574U JP S62121574 U JPS62121574 U JP S62121574U JP 845686 U JP845686 U JP 845686U JP 845686 U JP845686 U JP 845686U JP S62121574 U JPS62121574 U JP S62121574U
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- clock oscillator
- time
- set value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 6
- 238000005259 measurement Methods 0.000 claims description 3
- 230000000737 periodic effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Measurement Of Unknown Time Intervals (AREA)
Description
第１図は本考案による周期信号の乱れ検出器の
実施例を示す回路図、第２図は第１図の動作を説
明するためのタイミングチヤートである。
１……測定入力端子、２……信号変化検出回路
、３……時間測定用発振器、４……カウンタ回路
、５……時間設定回路、６……パルス幅チエツク
用回路、７，８……パルス幅の乱れ検出端子、９
……周期の乱れ検出端子。
FIG. 1 is a circuit diagram showing an embodiment of a periodic signal disturbance detector according to the present invention, and FIG. 2 is a timing chart for explaining the operation of FIG. 1... Measurement input terminal, 2... Signal change detection circuit, 3... Oscillator for time measurement, 4... Counter circuit, 5... Time setting circuit, 6... Pulse width check circuit, 7, 8... Pulse width disturbance detection terminal, 9
...Period disturbance detection terminal.
Claims (1)
て、時間測定用クロツク発振器と、測定対象の入
力信号の立上がりまたは立下がりを検出し、検出
出力と前記クロツク発振器出力の論理積条件によ
つてリセツトされる信号変化検出回路と、時間設
定可能な時間設定回路と、前記信号変化検出出力
によつて前記時間設定回路の設定値がセツトされ
、前記クロツク発振器のクロツクを計数して前記
セツト値になつたとき出力を発生するカウンタ回
路と、前記入力信号と前記カウンタ回路出力の論
理積条件によつて周期信号のパルス幅をチエツク
するパルス幅チエツク用回路とからなり、周期信
号の乱れと、周期信号のパルス幅を検出するよう
に構成したことを特徴とする周期信号の乱れ検出
器。 A detector for detecting disturbances in a periodic signal includes a clock oscillator for time measurement, detects the rise or fall of an input signal to be measured, and is reset according to an AND condition of the detection output and the output of the clock oscillator. a signal change detection circuit, a time setting circuit capable of setting a time, and a set value of the time setting circuit is set by the signal change detection output, and the set value is reached by counting the clocks of the clock oscillator. The counter circuit is composed of a counter circuit that generates an output when A periodic signal disturbance detector characterized in that it is configured to detect pulse width.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP845686U JPS62121574U (en) | 1986-01-24 | 1986-01-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP845686U JPS62121574U (en) | 1986-01-24 | 1986-01-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62121574U true JPS62121574U (en) | 1987-08-01 |
Family
ID=30792848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP845686U Pending JPS62121574U (en) | 1986-01-24 | 1986-01-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62121574U (en) |
-
1986
- 1986-01-24 JP JP845686U patent/JPS62121574U/ja active Pending
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