JPS6212148A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable standby currents to be reduced by changing over the charging-pump capacity of a charging-pump circuit as required. CONSTITUTION:The charging-pump capacity of a charging-pump circuit on the oscillator 1 side is increased because the oscillation frequency f1 of an oscillator 1 is set at a high value, and the charging-pump capacity of a charging- pump circuit on the oscillator 2 side is reduced because the oscillation frequency f2 of an oscillator 2 is set at a low value. Accordingly, the charging-pump circuit containing the oscillator 1 is operated when a chip is selected in a semiconductor device such as a semiconductor memory storage, and the charging-pump circuit including the oscillator 2 may be operated when the chip is not selected.

Description

[Detailed Description of the Invention] [Summary] The present invention uses a built-in charge pump circuit to reduce the substrate bias voltage. In semiconductor integrated circuit devices that supply
By providing a charge pump circuit whose pumping capacity is switched depending on the operating state of a circuit built into the semiconductor chip, for example, whether or not a memory is selected in a semiconductor memory device, the semiconductor chip can be When most of the circuits incorporated in the semiconductor chip are in operation, a large charge pump capacity is generated, and when the circuits incorporated in the semiconductor chip are hardly in operation, the charge pump capacity is reduced or Stop the charge pump operation so that normal operation will not be affected in any way.
Furthermore, power consumption during standby can be reduced.

[Industrial application field]

The present invention relates to an improvement in a semiconductor integrated circuit device having a charge pump circuit that generates a substrate bias voltage v0.

[Conventional technology]

It is conventionally known to drive a charge pump circuit with an oscillator output pulse to generate a substrate bias voltage V18, as can be seen, for example, in US Pat. No. 3,794,862.

In general, in an integrated circuit device to which a substrate bias voltage V■ is applied, when many of the circuits on the chip become operational, for example, when a chip is selected in a semiconductor memory device, A large substrate bias current IBM is required, but when the chip is not selected, that is, in a steady state, the substrate bias current 1118 is only required to compensate for junction leakage current, etc.

[Problem that the invention seeks to solve]

Even in an integrated circuit device that is equipped with a charge pump circuit to obtain the substrate bias voltage VllB as described above, the amount of substrate bias current rai+ flowing varies greatly depending on, for example, whether a chip is selected or not. Therefore, when a large substrate bias current 11111 is required, the capacity of the charge pump circuit must be large, and it also compensates for junction leakage current etc. in a steady state. Substrate bias current of about II
If the charge pump circuit is not required, the ability of the charge pump circuit may not be very large, but the substrate bias voltage V
It is possible to maintain BB at a predetermined value, and also ■. − Even with 〇, FE is within the range where the desired steady state can be maintained.
If the threshold voltage VLh of T is selected, there is no need to operate the charge pump circuit at all when a chip is not selected, for example.

Usually a charge pump with large charge pump capacity.
A large amount of power is consumed in the pump circuit. Therefore, for example, if a charge pump circuit that is capable of supplying the substrate bias current raa required when a chip is selected is kept in operation at all times, a considerable amount of power is wasted. .

In the present invention, for example, when a chip is selected, that is, when most of the circuits in the chip are in operation, the charge pump circuit is made to operate sufficiently, and when the chip is not selected, the charge pump circuit is made to operate sufficiently. In this case, the charge pump capability of the charge pump circuit is reduced or the charge pump operation is stopped, thereby making it possible to reduce the standby current.

[Means for solving problems]

In the semiconductor integrated circuit device of the present invention, the substrate bias voltage
. By providing multiple systems of charge pump circuits to supply the charge pump, or by making it possible to stop the charge pump operation as necessary even if there is a single charge pump circuit, the charge pump operation can be stopped as necessary. Pump circuit charge
The pump capacity can be changed as needed.

[Effect]

According to the above means, when most of the circuits in the integrated circuit device are in an operating state, for example when a memory of a semiconductor storage device is selected, the charge pumping capacity of the charge pump circuit is maximized. so that, and vice versa,
For example, if the memory is not selected, the charge
Since it is possible to reduce the pump capacity to a minimum or zero, there is no problem in performance during operations that require a charge pump, and moreover, power consumption in standby mode can be significantly reduced. It is something that can be done.

〔Example〕

FIG. 1 shows an explanatory diagram of a main part circuit of an embodiment of the present invention.

In the figure, 1 is an oscillator, 2 is a buffer circuit consisting of an inverter, 3 is a charge pump capacitor, 4 is a clamp transistor, 5 is a charge pump transistor, 6 is an inverter, 7 is an oscillator, and 8 is an inverter. 9 is a charge pump capacitor, 10 is a clamp transistor, 11 is a charge pump transistor, 12 and 13 are NOR gates, N1 to N4 are main nodes, and ■ indicates whether the memory is activated. A so-called chip that selects whether to go on standby
Select signal, Vllll is substrate bias voltage, 181
1 indicates a substrate bias current flowing from node N4 to the substrate.

FIG. 2 is a timing chart showing voltage waveforms at main nodes N1 to N4 to explain the operation of the embodiment of the present invention shown in FIG. 1, and the symbols used in FIG. The same symbols represent the same part or have the same meaning.

In the figure, VCC is the positive power supply level, O8 is the point at which oscillation starts (when the power is turned on), Vth (4) is the dark voltage of clamping transistor 4, and Vth (5) is the charge level.
The dark voltage of the pump transistor 5 is shown. Note that the waveform indicated by a broken line in the column for node N4 is a copy of the voltage waveform at node N3 for ease of comparison.

The operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2. Since the operation of the circuit is the same, only the side having the oscillator l will be explained.

Now, when the oscillator l oscillates, a pulse voltage waveform as seen at Nl in FIG. 2 appears at the node N1.

Next, a voltage waveform obtained by inverting the voltage waveform at the node N1 by the buffer circuit 2 appears at the node N2.

Next, the voltage waveform at the node N2 appears as an alternating pulse voltage waveform at the node N3 via the charge pump capacitor 3. That is, the voltage at the node N3 tends to rise as the voltage at the node N2 rises, but when the voltage at the clamping transistor 4 tries to rise from the ground level to the dark value voltage of the clamping transistor 4, the voltage at the clamping transistor 4 increases. 4 becomes conductive and is clamped, and in a state where the voltage is below the ground level, the clamping transistor 4 is reduced to the extent that it is cut off.

Here, the case where the voltage falls at node N3 will be explained in more detail.

At the beginning of oscillation, when the voltage at node N3 falls and becomes lower than the voltage at node N4, charge pump transistor 5 turns on, and charge flows from node N4 toward node N3. The amplitude of the voltage at node N3, that is, the amount of fall, is small, but if the oscillation is repeated enough, the charge at node N4 is released and an equilibrium state is reached, so the amplitude of the voltage at node N3 gradually increases. It saturates toward the amplitude determined by the following formula: Δ■, voltage amplitude Δv at node N3: voltage amplitude Cc at node N2: parasitic capacitance at node N3.

In such a state, as mentioned above, node N
4, the charge has been sufficiently discharged and an equilibrium state has been reached, so the constant voltage is applied to N4 in Figure 2, as shown by the solid line in the part marked with "after repeating oscillation an infinite number of times". appears, and this can be expressed as the substrate bias voltage VllIl
It is used as a.

By the way, in the above embodiment, the following relationship is set between the oscillation frequency f1 of the oscillator 1 and the oscillation frequency f2 of the oscillator 7: f,>f2 (actually, f, >>f is fine). The oscillator 1 oscillates when the chip select signal C8 is at a low level, and the oscillator 7 oscillates when the chip select signal C8 is at a high level.

Now, since the oscillation frequency f1 of the oscillator 1 is high, the charge pump circuit on the oscillator 1 side has a large charge pumping ability, and since the oscillation frequency f2 of the oscillator 2 is low, the charge pump circuit on the oscillator 2 side has a high charge pump capacity. The charge pumping capability of the circuit is reduced. Therefore, for example, in a semiconductor memory device, when a chip is selected, the oscillator 1
If the chip is not selected, the charge pump circuit including the oscillator 2 may be operated.

FIG. 3 shows the chip select signal σ3 as explained above.
3 is a timing chart showing the relationship between substrate bias current fall and substrate bias voltage Vllll+ when the capacity of the charge pump is switched in FIG.

In FIG. 3, it is assumed that the oscillation of the oscillator 7 has already stabilized.

As is clear from FIG. 3, in this embodiment, when the chip select signal σ is high level, the chip is not selected, and when it is low level, the chip is selected. When the chip select signal C is at high level, the NOR gate 12
The output of is fixed at low level. Therefore, oscillator 1
The feedback loop is cut and no oscillation occurs.

However, at this time, the output of the inverter 6 is at a low level, so a feedback loop of the oscillator 7 is formed via the NOR gate 1°3, the oscillator 7 oscillates, and the value of the substrate bias current at this time is becomes 1111+1.

Conversely, when the chip select signal n goes low, one input of the NOR gate 13 is fixed at a high level, and one input of the NOR gate 12 is fixed at a low level. Therefore, a feedback loop is formed in oscillator I, and the feedback loop is broken in oscillator 7, so that
Oscillator 1 oscillates. As mentioned above, since f>f2, when the chip select signal ■=low level, the substrate bias current 111N1 is larger than III
! flows.

In this way, l1ll12 flows when the chip is selected, and l1l11 flows when the chip is not selected, but when the chip is not selected, the desired substrate bias voltage V□ can be obtained even with a small substrate bias current value. Regardless, the substrate bias voltage Vl11 remains constant.

In the embodiment described with reference to FIG.
We used two charge pump circuits, one with a large pumping capacity and one with a small charge pumping capacity.For example, we used a charge pump circuit with a large charge pumping capacity, that is, an oscillator l. It is also possible to use only the charge pump circuit on the containing side, and to disable that charge pump circuit in a steady state.

〔Effect of the invention〕

The semiconductor integrated circuit device according to the present invention is configured to include a pump circuit whose pumping capacity for generating a substrate bias voltage can be switched in accordance with the operating state of a circuit incorporated in a semiconductor chip. .

According to this configuration, the pumping ability of the pump circuit for generating a substrate bias voltage can be adjusted depending on the operating state of a circuit built into a semiconductor chip, for example, in the case of a semiconductor memory device, whether a memory is selected or not. Since it can be switched, it can generate a large pumping capacity when the circuit in the semiconductor chip requires a large substrate bias current, and it can also reduce, for example, junction leakage current when the circuit is in a steady state where it does not operate. It is possible to generate a compensating amount of pumping capacity or to stop the pumping action to save power consumption of the pumping circuit.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the main circuit of an embodiment of the present invention, Fig. 2 is a timing chart of voltage waveforms at main nodes to explain the operation of the embodiment shown in Fig. 1, and Fig. 3 is 11 when the chip is selected and when the chip is not selected.
11+ and V811 are shown respectively. In the figure, 1 is an oscillator, 2 is a buffer circuit, 3 is a charge pump capacitor, 4 is a clamp transistor, 5 is a charge pump transistor, 6 is an inverter, 7 is an oscillator, 8 is a buffer circuit, 9 is charge/
Pump capacitor, lO is clamp transistor,
11 are charge pump transistors, N1 to N4
is a node, σ3 is a chip select signal, Vllll+ is a substrate bias voltage, and tas is a substrate bias current.

Claims (2)

[Claims] (1) A semiconductor integrated circuit device comprising a charge pump circuit whose charge pump capability for generating a substrate bias voltage can be switched in accordance with the operating state of a circuit incorporated in a semiconductor chip. (2) The semiconductor integrated circuit device according to claim 1, wherein the charge pumping capacity of the charge pump circuit is made larger when a semiconductor integrated circuit chip is selected than when it is not selected.