JPS621184A - Semiconductor device - Google Patents

Abstract

PURPOSE:To speed up an action and to prevent the influence of a minority carrier, the occurrence of a parasitic MOSFET and latch-up at turning on a power source in terms of a semiconductor memory including a CMOS circuit by incorporating a substrate bias voltage generator circuit. CONSTITUTION:Receiving a substrate bias voltage -Vbb formed by the sub strate bias generator circuit VBG, a voltage detecting circuit VC monitors that said voltage -Vbb is made to a desired negative potential, and transmits the detection output VS to the input circuit of a timing generator circuit TG. Namely, until the substrate bias voltage -Vbb is made to the desired negative potential after the power source is turned on, the fetch of a row address strobe signal RAS being a substantial chip selecting signal is inhibited by the detection output, in other words, the transmission of a signal, the inverse of RAS to an internal circuit is inhibited even if the signal, the inverse of RAS is made at a low level, and a memory access is invalidated.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor device, and for example, a peripheral circuit is configured by a CMO3 (complementary MOS) circuit,
Dynamic type R with built-in substrate bias voltage generation circuit
It relates to technology that is effective for use in AM (Random Access Memory).

[Background technology]

In order to reduce power consumption and increase high-speed operation in dynamic RAM, peripheral circuits such as address buffers and address decoders are implemented using P-channel MOSFETs (insulated gate field effect transistors) and N-channel MOSFETs.
It is known to use a CMO3 circuit configured in combination with T (for example, Nikkei McGraw-Hill 1985
(Refer to “Nikkei Electronics,” February 11, 2015, pages 243 to 263).

By the way, a dynamic memory cell retains stored information in the form of whether or not there is charge in the information storage campacitor. The charges accumulated in the capacitor combine with minority carriers generated in the substrate and are eliminated. Therefore, it is necessary to refresh the stored information by reading it out before it is lost, amplifying it, and writing it into the same memory cell again. If the refresh cycle is short, there is a problem that the time for reading and writing to the dynamic RAM is limited and reduced. Therefore, in order to lengthen the refresh period (information retention time of the memory cell), it is effective to supply a negative bias voltage to the substrate to absorb the minority carriers.

For example, a dynamic RAM configured with an N-channel MOSFET has a built-in substrate bias circuit (for the substrate bias circuit, see, for example, Japanese Patent Application Laid-Open No. 55-13566).

However, the dynamic type R with CMO5N path
When a substrate bias circuit is built into an AM, the following problem occurs. Immediately after the power is turned on, the driving current of the substrate bias circuit is small, so the potential of the P-type substrate becomes a positive potential (for example, about +0.6 V) due to capacitive coupling between the substrate and the N-type well region to which the power supply voltage Vcc is supplied. I was lifted up. As a result, N
Since the source, drain, and substrate of the channel MOSFET are placed in a state extremely close to forward bias, latch-up is likely to occur. If a triggering current is supplied to any of the above regions in such an unstable state, there is a risk that the parasitic thyristor element will unexpectedly be turned on, resulting in latch-up. In particular, in a dynamic RAM, inputting the low level of the row address strobe signal RAS may cause a 7-up. When the memory access operation is activated by the signal RAS, the internal circuits are simultaneously activated. That is, current flows through the plurality of MOS FETs that constitute the internal circuit. This generates a substrate current in the substrate raised to the positive potential. This substrate current further increases the potential of the substrate, thereby forward biasing the substrate and the source and drain of the N-channel MOSFET.

Therefore, by inputting the signal RASO low level,
- There is a problem in that the substrate current generated due to internal circuits operating simultaneously tends to trigger latch-up.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory that has a simple configuration and prevents latch-up from occurring when power is turned on.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical embodiments of the invention disclosed in this application is as follows. That is,
Monitors the output voltage of the substrate bias ordering circuit that supplies the back bias voltage to the substrate, and prohibits the capture of the actual chip selection signal supplied from the external terminal until the potential is set to the desired potential. It is something.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment in which the present invention is applied to a dynamic RAM. Each circuit element in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known CMO3 integrated circuit manufacturing technique. In the figure, the MOSFET with a straight line added between the source and drain is a P-channel type, and
It is distinguished from the above-mentioned N-channel MOSFET without a straight line.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MOS
The FET has a source region, a drain region formed on the surface of the semiconductor substrate, and a gate made of polysilicon formed on the surface of the semiconductor substrate between the source region and the drain region with a thin gate insulating film interposed therebetween. Consists of electrodes. The P-channel MO3FET is formed in an N-type well region formed in the semiconductor substrate. Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MOSFETs formed thereon.

The N-type well region constitutes the substrate gate of the P-channel region S FET formed thereon. The base i-gate or N-type well region of P-channel MO3FET (7) is coupled to power supply terminal Vcc in FIG. The substrate bias voltage generation circuit VBG generates a negative bank bias voltage -vbb to be supplied to the semiconductor substrate. As a result, a bank bias voltage is applied to the substrate gate of the N-channel region SFET, that is, the semiconductor substrate, and the parasitic capacitance between the source, drain, and substrate is reduced, resulting in faster circuit operation. be able to. Furthermore, since minority carriers generated in the substrate can be absorbed, the refresh period can be lengthened.

The more specific structure of an integrated circuit can be roughly explained as follows.

That is, of the surface portion of a semiconductor substrate made of single crystal P-type silicon and on which an N-type well region is formed, other than the surface portion that is used as an active region, in other words, the semiconductor wiring region, the capacitor formation region, and the N-channel and A relatively thick field insulating film formed by a known selective oxidation method is formed in areas other than the source, drain, and channel forming region (gate forming region) of the P-channel MOSFET. Although the capacitor formation region is not particularly limited, there is a relatively thin insulation I! on the capacitor formation region. 2! A first polysilicon layer is formed with an oxide film interposed therebetween. The first polysilicon layer extends over the field insulating film.

A thin oxide film formed by thermal oxidation of the first polysilicon layer is formed on the surface of the first polysilicon layer. A channel is formed on the surface of the semiconductor substrate in the capacitor formation region by forming an N-type region by ion implantation or by supplying a predetermined voltage.

As a result, a capacitor consisting of the first polysilicon layer, a thin insulating film, and a channel region is formed. The first polysilicon layer on the field oxide film is regarded as a type of wiring.

A second polysilicon layer to serve as a gate electrode is formed on the channel formation via a thin gate oxide film. This second polysilicon layer extends over the field insulating film and over the first polysilicon layer. Although not particularly limited, word lines and dummy word lines in a memory array, which will be described later, are constructed from a second polysilicon layer.

Source, drain, and semiconductor wiring regions are formed on the surface of the active region not covered by the field insulating film and the first and second polysilicon layers by a known impurity doping technique that uses them as an impurity doping mask. .

A relatively thick glabellar insulating film is formed on the surface of the semiconductor substrate including the first and second polysilicon layers, and a conductor layer made of aluminum is formed on this glabellar insulating film. . The conductor layer is electrically coupled to the polysilicon layer and the semiconductor region through a contact hole provided in the insulating film below. A data line in a memory array, which will be described later, is composed of a conductor layer extending on this glabella insulating film, although it is not particularly limited.

The surface of the semiconductor substrate including the top of the glabella insulating film and the top of the conductor layer is covered with a final passivation film made of a silicon nitride film and a phosphosilicade glass film.

Although not particularly limited, the memory array M-ARY is of a two-intersection (folded bit line) type.

FIG. 1 specifically shows the pair of rows. A pair of complementary data lines (bit lines or digit lines) D and D arranged in parallel are used to input and output each of a plurality of memory cells each composed of an N-channel type address selection MO3FBTQm and an information storage capacitor Cs. As shown in the figure, nodes are distributed and connected with a predetermined regularity.

The precharge circuit PC is constituted by a switch MO3FET provided between the complementary data line D and the N-channel MO3FET Q5 shown as a representative. This MOSFET Q5 is turned on when the chip is not selected by supplying the precharge signal φpc generated when the chip is not selected to its gate. As a result, in the previous operation cycle, a complementary data line is generated by the amplification operation of the sense amplifier SA, which will be described later.

The high level and low level of D are short-circuited to form a complementary data line, and D is set to a precharge voltage of approximately Vcc/2. Note that before the RAM is brought into a chip non-selected state and the precharge MO3FETQ5 and the like are turned on, the sense amplifier SA is brought into a non-operating state. This allows the complementary data line mentioned above to be established.

D maintains a high level and a low level in a high impedance state. Furthermore, when the RAM is brought into operation, the precharge MOSFET Q5 and the like are turned off before the sense amplifier SA is brought into operation. As a result, the complementary data MD and D maintain the half precharge level in a high impedance state.

In such a half precharge method, since the complementary data line D is formed by simply shorting the high level and low level of D, power consumption can be reduced. In addition, in the amplification operation of the sense amplifier SA, the complementary data line D changes in common mode, such as high level and low level, centering on the precharge level, so the noise level generated by capacitive force γ bling can be reduced. This can be reduced.

The unit circuit USA of the sense amplifier SA is shown as an example, and includes P-channel MO3FETQ7. Q9 and
N-channel MOSFETQ&.

QB, and its pair of input/output nodes are connected to the complementary data line.

It is connected to D. The latch circuit may include, but is not limited to, a parallel P-channel MOSFET.
QI 2. Power supply voltage Vcc is supplied through Ql 3, and parallel N-channel MO3FET QI O,Ql
The ground voltage Vss of the circuit is supplied through 1. These power switch MOSFETs QIO, Ql 1 and MO5FE'r'Q12. Q13 is commonly used for launch circuits (unit circuits) similarly provided for other rows in the same memory mat. In other words, the sources PS and SN of the P-channel MO3FET and N-channel MOSFET in the latch circuit in the same memory mat are commonly connected.

In the operation cycle, complementary timing pulses φpal and φpal that activate the sense amplifier SA are applied to the gates of the MOSFETs QIO and Q12, and the MOSFETs
SFETQI 1. A complementary timing pulse φpa2, 11>I)a2, which is delayed from the timing pulse φpal and $pal, is applied to the gate of Ql3. By doing this, the sense amplifier S
The operation of A can be divided into two stages. timing pulse φp
When aLφpal is generated, that is, in the first stage, MO3FE with relatively small conductance
Due to the current limiting effect of TQIO and Q12, the minute read voltage applied between the pair of data lines from the memory cell is amplified without undergoing undesired level fluctuations. After the difference in complementary data line potential is increased by the amplification operation in the sense amplifier SA, the timing pulse φ
When pa2+φpa2 is generated, that is, when entering the second stage, MO3FE with a relatively large conductance
TQII and Q13 are turned on.

The amplification operation of the sense amplifier SA is performed using MOS FETQl.
1 and Q13 are turned on. By performing the amplification operation of the sense amplifier SA in two stages in this way, it is possible to read data at high speed while preventing undesired level changes in the complementary data line.

Although not particularly limited, the row decoder R-DCR is configured by a combination of two divided row decoders R-DCR1 and R-DCR2.

In the figure, one circuit (four word lines) of the second row decoder R-DCR2 is shown as a representative. According to the configuration shown in the figure, N-channel MOSFETs Q32 to Q34 receiving address signals 12 to am The word line selection signals for the four lines are formed by a 1'JAND (NAND) circuit formed by a CMO3 circuit including P-channel MO3FETs Q35 to Q37. The output of this NAND circuit is inverted by a CMOS inverter IVI, and then passed through N-channel cut MOSFETs Q28 to Q31 as an N-channel transmission gate as a switch circuit.
It is transmitted to the gates of MOSFETs Q24 to Q27.

The first row decoder R-DCR1 receives 2-bit complementary address signals aQ, aQ, although its specific circuit is not shown.
Four types of word line selection timing signals φx00 to φXll are generated from the word line selection timing signal φX by the decode signals formed by the word line selection timing signals φX and φX. These word line selection timing signals φx00 to φ-xl
l is transmitted to each word line via the transmission gate MOSFETs Q24 to Q27.

Although not particularly limited, when the address signals aO and al are at low level, the timing signal φχoo
It is set to high level in synchronization with the timing signal φX. Similarly, timing signals φx01, φxlo and φx,1
1 is set to high level in synchronization with timing signal φX when address signals D0 and al, aO and als, aQ and τl are set to low level, respectively.

As a result, the address signals a1 and Tl are transmitted to the word line group (WO, Wl, hereinafter referred to as the first word line group) corresponding to the memory cell coupled to the data line among the plurality of word lines. It is regarded as a kind of word line group selection signal for identifying a word line group (W2, W3, hereinafter referred to as a second word line group) corresponding to a memory cell coupled to a data line.

By dividing the row decoder into two like row decoders R-DCR1 and R-DCR2, the row decoder R-
The pitch (interval) of DCR2 and the pitch of word lines can be matched. As a result, no wasted space is created on the semiconductor substrate. N-channel MO3FETs Q20 to Q23 are provided between each word line and the ground potential, and by applying the output of the NAND circuit to their gates, the word lines are fixed at the ground potential when not selected. be.

Although not particularly limited, the word line may have a far end side (
MOSFET for reset on the end opposite to the decoder side)
QI-Q4 are provided, and when these MOS FETs Q1-Q4 are turned on in response to a reset pulse φρ-, the selected word line is reset to the ground level from both ends thereof.

Column switch C-5W is shown as a representative N
Channel MO5FE"l"Q42. Like Q43,
The complementary data line, D, and the common complementary data line, CD, are selectively coupled. These MOSFETQ42. Q4
A selection signal from the column decoder C-DCR is supplied to the gate of No. 3.

The row address buffer R-ADB is put into an operating state by a timing signal (not shown) generated by a timing generation circuit TG, which will be described later, based on a row address strobe signal RAS supplied from an external terminal, and in that operating state, the above-mentioned Address signals AO to A supplied from external terminals in synchronization with row address strobe signal RAS
When m is taken in and held, internal complementary address signals 10 to am are formed and the row address decoder R
- Inform DCR1 and R-DCR2. Here, the address signal AO supplied from the external terminal, an internal address signal aO having the same phase, and an internal address signal TO having the opposite phase are collectively expressed as a complementary address signal 0 (hereinafter,
same). Row address decoders R-DCR1 and R-DC
R2 is the complementary address signal 10~am as described above.
is decoded and a word line selection operation is performed in synchronization with the word line selection timing signal φX.

On the other hand, the column address buffer C-ADB is put into an operating state by a timing signal (not shown) generated by a timing generation circuit TG, which will be described later, based on a column address strobe signal CAS supplied from an external terminal. At this time, the address signal AOyAn supplied from the external terminal is taken in in synchronization with the column address strobe signal "4 CAS", and when it is held, an internal complementary address signal O-50 is formed and the column address decoder C- Tell DCH.

Column decoder C-0CR has its column selection timing controlled by data line selection timing signal φyi, and decodes complementary address signal aOwan supplied from column address buffer C-ADB to select column switch C-5W. Forming the selection signal to be supplied.

In addition, in the same figure, the row address buffer R-AD
B and column address buffer 1C-ADB are collectively represented as address buffer R, C-ADB.

An N-channel precharge MOSFET Q44 constituting a similar precharge circuit as described above is provided between the common complementary data lines CD and CD. The common complementary data lines CD and CD are connected to the sense amplifier US of the above unit.
A pair of input and output terminals of a main amplifier MA having the same circuit configuration as A is coupled. The output signal of this main amplifier is sent to the external terminal Do via the data output buffer DC)B.
Sent to ut. In the case of a read operation, the data output buffer DOB is activated by the timing signal φr-, amplifies the output signal of the main amplifier MA, and sends it out from the external terminal I10. Note that in the case of a write operation, the output of the data output buffer DOB is placed in a high impedance state by the timing signal 7r-.

The common complementary data lines CD, CD are coupled to the output terminal of the data input buffer sofa DIB. If the operation includes iF, the data driver DIB uses its timing signal φ
write into the selected memory cell by forming a complementary write signal in accordance with the write signal supplied from the external terminal Din and transmitting it to the common complementary data lines CD, CD. It will be done. In the case of a read operation, the output of the data driver sofa DIH is brought into a high impedance state by the timing signal φr-.

As shown above, MOS FETQ for address selection
In a write operation to a dynamic memory cell consisting of an information storage capacitor Cs and an information storage capacitor Cs, a full write is performed to the information storage capacitor Cs. In order to prevent a level loss of the write high level to the capacitor Cs, a word line bootstrap circuit (not shown) activated by the word line selection timing signal φX is provided. This word line boot strap circuit uses the word line selection timing signal φX and its delayed signal to set the high level of the word line selection timing signal φX to a high level equal to or higher than the power supply voltage Vcc.

The various timing signals described above are generated by the following timing generation circuit TG. The timing generation circuit TG is
The main timing signals etc. shown as the representative above are formed. That is, this timing generation circuit TO receives address strobe signals RAS and CAS supplied from external terminals and a write enable signal WE, and forms the series of various timing pulses described above.

The circuit symbol REFC is an automatic refresh circuit and includes a refresh address counter and the like. This automatic refresh circuit REFC is connected to address slope signals RAS and CAS, although not particularly limited.
When the column address strobe signal CAS is set to low level before the row address strobe signal RAS is set to low level, the logic circuit receiving the row address strobe signal CAS determines that it is a refresh mode, and the address counter uses the row address strobe signal RAS as a clock. Refresh address signal aQI formed by the circuit
am' is sent. This refresh address signal a
O゛~am'' is transmitted to the row address decoder circuits R-DCRI and R-DCR2 via the row address buffer R-ADB having a multiplexer function.For this reason, the refresh control circuit REFC, in the refresh mode, A control signal for switching the address buffer R-ADH is generated (not shown), thereby generating refresh address signals aO° to am'.
A refresh operation is performed by selecting one word line corresponding to (CAS before RAS refresh).

The voltage detection circuit VC is the substrate bias generation circuit VBG.
In response to the substrate bias voltage −vbb formed by
It monitors that it is set to a desired negative potential, and transmits the detection output (1)S to the input circuit of the timing generation circuit TG. That is, until the substrate bias voltage -vbb is set to the desired negative potential immediately after the power is turned on, the detection output is used as a substantial chip selection signal (memory access signal) in the above-mentioned multi-address type Guinamic RAM. In other words, even if the RAS signal is set to low level, it is prohibited from being transmitted to the internal circuit, thereby invalidating memory access.

FIG. 2 shows a circuit diagram of an embodiment of the input circuit included in the substrate bias voltage generation circuit VBG, voltage detection circuit VC, and timing ordering circuit TO.

In the same figure, the inverter circuits IV2 to IV6 are configured from CMOS circuits, although not particularly limited, and are applied between the Wi source terminal Vcc, which constitutes the external terminal of the integrated circuit, and the reference potential terminal or the ground terminal, such as +5V. It is operated from a positive supply voltage.

The substrate bias voltage generation circuit VBG generates a negative bank bias voltage -vbb to be supplied to the semiconductor substrate. This causes a negative back bias voltage to be applied to the substrate gate of the N-channel MOSFET.

The substrate bias voltage generation circuit VBG of this embodiment receives an oscillation output signal from an oscillation circuit OSC constituted by three (an odd number is sufficient) inverter circuits IV2 to IV4 connected in series in a ring shape. CMOS inverter circuit that performs waveform shaping and amplification IV5. It consists of IV6 and the following rectifier circuit or level conversion circuit. In the rectifier circuit, the oscillation pulse obtained from the output of the CMOS inverter circuit IV6 is transmitted through a capacitor C1 that receives a signal at one electrode e1, and another electrode e of this capacitor C1.
2 and the circuit ground potential point Vss, and this capacitor C1.
A diode-type MOSFET Q51 is provided between the other electrode e2 and the substrate. Between this substrate and the ground potential point Vss of the circuit, there is a parasitic capacitance @C2 consisting of junction capacitance, wiring capacitance, etc. between the source of the MOSFET and the substrate. The above diode type MOS
FET Q50 is turned on by the positive voltage supplied via capacitor C1 when the output pulse from inverter circuit IV6 is at a high level (power supply voltage Vcc). As a result, the capacitor C1 is precharged with a high level. When the oscillation pulse is set to a low level (ground potential of the circuit), that is, when one electrode e1 of the capacitor C1 is set to a low level, the capacitor C1 The other electrode, 32, is -(Vcc-Vt
h) negative potential. Here, vth is MOSFETQ
50 threshold voltage. This negative potential turns on the diode-type MO3FETQ51. Accordingly, the negative potential applied to the electrode e2 is
It is transmitted to the parasitic capacitance C2 via TQ51. That is, a substrate bank bias voltage of -vbb is applied to the substrate.

A voltage detection circuit VC is provided to detect (monitor) whether the substrate bias voltage -vbb is set to a predetermined negative potential. Although the voltage detection circuit VC is not particularly limited,
Level detection section of substrate bias voltage and MO3FI3TQ
61 and Q62, and NAND (
It consists of a NAND gate circuit G1, a MOSFET Q63, and a resistor R. The level detection section consists of the following: The P-channel MO3FET Q56 is constantly turned on by constantly supplying the circuit ground potential to its gate, and is made to act as a load resistor.

This MO3FETQ56 is connected in series with an N-channel MO8FETQ57 for output level clamping.This MO3FETQ57 is constantly turned on by constantly supplying the circuit ground potential to its gate. Between the drain of the MOSFET Q57 and the substrate (-Vbb), an N-channel MO3, each having a threshold voltage vth and in the form of a diode, is connected.
CMOSF installed in series configuration of FETQ58 and Q59
ETQ58. Q59 substantially constitutes a level shift circuit.

The operation of this level detection section is as follows.

The absolute value of the substrate bias voltage -vbb is the diode type MO3FETQ58. When the level is lower than the combined threshold voltage 2Vth by Q59, these (71MO
3FETQ58. Q59 is turned off. As a result, the potential at the connection point between the MO3FETs Q56 and Q57 is brought to a high level such as the power supply voltage Vcc.

On the other hand, the absolute value of the substrate bias voltage -vbb is the diode type MO3FETQ58. When set to a level greater than the combined threshold voltage 2Vth by Q59,
These MO3FETQ58°Q59 are turned on. Accordingly, the potential at the connection point of the MOSFETs Q56 and Q57 is different from the ground potential of the circuit.
It is set to a low level which is increased by the threshold voltage vth of Q57. Note that from the above power supply voltage Vcc to MOS F
The current flowing to the substrate through ETQ56 to Q59 reduces the substrate bias voltage -vbb in absolute value. In order to prevent such voltage drop, and the above MOSFET
Q58. In order to form the above-mentioned low level by the combined conductance of Q59 and MOSFET Q57, the load MO3FET Q56 is set to have an extremely small conductance, that is, an extremely small conductance that allows only a small amount of current to flow.

Further, in a normal operating state, the substrate bias voltage -vbb is lowered by the leakage current flowing to the substrate, so that the MO3FETs Q58 and Q59 are prevented from being turned off.

In other words, the threshold voltage 2Vth is set to be smaller in absolute value than the lowest voltage of the substrate bias voltage -vbb.

This ensures that the substrate bias voltage -vb under normal operating conditions
Even if b fluctuates, the MO3FETQ58°Q59 is maintained in the on state.

The high level and low level of the detection output of the level detection section as described above are determined by the following level determination circuit. The level judgment circuit is a P-channel MOSFETQ61
, an N-channel MO3FETQ62, and a P-channel MO3FETQ63 for feedback. This CMOS inverter circuit is a hysteresis circuit, although not particularly limited, in order to prevent an oscillatory determination signal with an extremely narrow pulse width from being outputted therefrom. That is, the gate of MOSFET Q63 provided between the power supply voltage Vcc and the output of the CMOS inverter circuit is connected to a NOR circuit whose one input is the output of the CMOS inverter circuit.
) The output VS of the gate circuit Gl is supplied.

The operation of this level determination circuit is as follows.

If the output of level [IIfS is inverted from high level to low level (from low level to high level), MO
Positive feedback by 3FET Q63 quickly inverts the output of the CMOS inverter circuit (Q61 and Q62) to high level (low level).

Although not particularly limited, the output of this CMOS inverter circuit is transmitted to one side of the NOR gate circuit G1. The other input of this NOR gate circuit G1 is applied with the ground potential of the circuit via a high resistance R such as polysilicon. As a result, in the NOR gate circuit G1, a low level is supplied to the other input in the normal operating state.
It essentially operates as an inverter circuit. The output 1S of this NOR gate circuit G1 is inputted to the timing generation circuit TG as an output of the detection circuit VC. The output vS is supplied on the one hand to the gate of a P-channel MO3FETQ63 provided between its input and the power supply voltage Vcc.

The voltage detection output VS formed by the NOR gate circuit G1 is supplied to one input of a NOR gate circuit G2, which is an input gate of the timing generation circuit TG. The other input of this NOR gate circuit G2 is supplied with a row address strobe signal RAS supplied from an external terminal.

The output signal RAS of this NOR gate circuit G2 is transmitted to the timing generation circuit TO. Noah gate circuit G2
is a control gate (switch) that determines whether or not to transmit the row address strobe signal RAS to the internal circuit in response to the detection output of the detection circuit VC.

In this embodiment, the detection output of the level detection section is kept at a high level until the substrate bias voltage generation circuit VBG starts operating when the power is turned on and its output voltage -vbb is lowered to a predetermined potential or less. . Since the NOR gate circuit Gl works as an inverter circuit in normal operation, the detection output vS of the detection circuit VC is set at a high level. As a result, the output of the NOR gate circuit G2 is fixed at a low level. Therefore, row address strobe signal R
AS is not transmitted to the gate circuit G2 and subsequent parts of the timing generation circuit TG. In other words, in a multi-address type memory, the row address strobe signal RAS, which is essentially a chip selection signal, is not accepted by this memory.

The substrate bias voltage generation circuit operates and its output voltage -
When the potential of vbb is made sufficiently low, the detection output of the level detection section changes from high level to low level. In response to this, the output vS of the detection circuit VC is set to a low level. As a result, the NOR gate circuit G2 functions as an inverter circuit. Therefore, the NOR gate circuit G2 outputs a signal obtained by inverting the row address strobe signal RAS, which is one of its inputs, as its output signal RAS.

In addition, in order to realize a stress test, etc. in blowing of a RAM completed on a semiconductor wafer, during the blowing test, a power supply voltage such as Vcc is applied from a probe to a pad P connected between the gate circuit G1 and the resistor R. A high level (logic "1") is supplied. As a result, the output signal VS of the NOR gate circuit G1 is set to a low level regardless of the substrate bias voltage -Vbb. In response, the output signal RAS of the NOR gate circuit G2 is set to a level according to the address strobe signal RAS supplied from the external terminal. Thus, during the probing, the address strobe signal τAS is set to low level, thereby making it possible to access the RAM regardless of the substrate potential. The rose l-P can be connected to the detection circuit VC as required, especially during the probing test.
This is to stop the function of

In this embodiment, the substrate bias generation circuit VGG starts operating when the power is turned on, and its substrate bias voltage -vb
Until b is lowered below a predetermined potential, input of the row address strobe signal RAS, which is the actual chip selection signal, is prohibited, so the substrate potential is in an unstable state where it is at a positive potential, etc. Since the operation of the internal circuit is prohibited, it is possible to prevent latch amplifiers caused by unexpected parasitic thyristor elements. Note that in a CMO3 circuit, a parasitic thyristor element consisting of an N-channel MO3FET, a P-channel MOSFET, and a well region is inevitably constructed, but by setting the layout appropriately, it can be configured as described above. Latch-up does not occur immediately if the potential of the substrate is set to a positive potential immediately after power is turned on.

〔effect〕

(By incorporating a substrate bias voltage generation circuit in a semiconductor memory including a 11CM OS circuit, it is possible to increase the operation speed and prevent the influence of minority carriers, as well as prevent the generation of parasitic MOS FETs between elements. By monitoring the bias voltage and inhibiting the operation of the circular portion circuit until it reaches a desired potential, it is possible to reliably prevent the latch amplifier from occurring when the power is turned on.

(2) By providing a pad and disabling the monitor output during probing, it is possible to carry out stress tests on semiconductor memories.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, a substrate bias circuit can be configured with a circuit that has only a small current supply capability to compensate for leakage current in a chip non-selected state, and a circuit that has a relatively large current supply capability during memory access, so that it can be used in standby mode. It may also be intended to reduce power consumption. The oscillation circuit is not limited to a ring oscillator, but may be a signal generation circuit such as a clock pulse generation circuit that receives an output from an original oscillation circuit.

The voltage detection circuit VC shown in FIG. 2 is not limited to this. N-channel MO3FETQ5 for level clamp
7 may be omitted.

In this case, the ground potential of the circuit is supplied to the gate of N-channel MOSFET Q5B. Also, P channel M
A no-gate circuit Gl that may use a high resistance layer made of polysilicon layer in place of the OSFET Q56.
In this case, the stopping function of the detection circuit VC during probing may be omitted, that is, the pulse P and the resistor R may be omitted, and an inverter circuit may be used. In this case, by inserting a suitable gate circuit between the output of the detection circuit VC and the input of the timing generation circuit, it is possible to add the same function of stopping the detection circuit VC during probing as described above. for example,
The above gate circuit has the output of the detection circuit VC as one input, the ground potential via the high resistance R as the other input, and a NAND (NAN) with the pad P connected to the other input.
D) It may be a gate circuit and an inverter circuit that receives the output. The form of this gate circuit is based on the row address strobe signal RAS of the first stage of the timing generation circuit TG.
It may be changed depending on the form of the gate circuit that receives the signal.

The pad P may be used as an external terminal of the memory, or may be a pad used only during probing, for example, not used as an external terminal.

The signal that the NOR gate circuit G2 receives from the external terminal is not limited to the row address strobe signal RAS, but may be any substantial chip selection signal.

NOR gate circuit G that receives this substantial chip selection signal
2 does not need to be provided in the timing generation circuit TG,
It does not have to be the first stage circuit that receives the RAS signal of the timing generation circuit TG. This can be changed by designing a layout that does not cause latch-up of the 0M05 circuit.

The substrate in substrate bias is not limiting. For example, when a back bias voltage is applied to a well region formed in a semiconductor substrate, the well region is considered to be the substrate in the substrate bias.

It is not essential whether the semiconductor memory itself is formed on one independent semiconductor substrate or not.

A semiconductor memory formed together with a circuit such as a microprocessing unit on one semiconductor substrate also constitutes a semiconductor memory within the meaning of the present invention.

Furthermore, the reference voltage required for the read operation of the memory cell of the dynamic RAM may be formed using a dummy cell. Furthermore, the specific circuit configurations of other peripheral circuits constituting the dynamic RAM can take various embodiments. for example,
The address signals may be supplied from independent external terminals. In this case, its operation/non-operation is controlled by the chip selection signal. An automatic refresh circuit is not particularly required.

In addition to the dynamic RAM, the semiconductor memory in which the substrate bias circuit is built-in includes a MO, which is formed on the substrate by supplying a back bias to the substrate.
Since the parasitic capacitance of the SFET is reduced, the operation speed can be increased, and the threshold voltage of the parasitic MO3FET constructed between the elements can be increased. Good too.

[Application field]

The present invention can be widely used in various semiconductor memories including a CMOS circuit and a substrate bias pressure generation circuit. Furthermore, the present invention provides a semiconductor device comprising an 0M05 circuit and a substrate bias voltage ordering circuit, which enables standby (
It can also be used in semiconductor devices (for example, microcomputers, etc.) in which the internal circuit starts operating substantially when the sleeve state is removed.

[Brief explanation of the drawing]

Figure 1 shows a dynamic RAM to which this invention is applied.
Circuit Diagram Showing One Embodiment FIG. 2 is a circuit diagram showing one embodiment of the input circuit included in the substrate bias generation circuit, voltage detection circuit, and timing generation circuit.

Claims (1)

[Claims] 1. N-channel MOSFET and P-channel MOSF
A CMOS circuit configured in combination with an ET, a substrate bias generation circuit that receives an oscillation output signal and supplies a back bias voltage to the substrate, a voltage detection circuit that receives the output voltage of the substrate bias voltage generation circuit, and this voltage. 1. A semiconductor device comprising: an input circuit that prohibits reception of a substantial chip selection signal supplied from an external terminal until the bias voltage reaches a desired voltage based on a detection output of a detection circuit. 2. The voltage detection circuit includes a MOSFET whose gate is coupled to the ground potential of the circuit and whose source is supplied with a voltage according to the substrate bias voltage, and a load means provided at the drain of the MOSFET. A semiconductor device according to claim 1, characterized in that: 3. The input circuit according to claim 1 or 2, wherein the input circuit has a function of invalidating the detection signal of the voltage detection circuit by the voltage signal applied to the pad. Semiconductor equipment. 4. The semiconductor device according to claim 1, 2 or 3, wherein the CMOS circuit constitutes a peripheral circuit in a dynamic RAM.