JPS62118386A - Method and apparatus for processing video signal of still image - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a video signal processing method for a still image and an apparatus therefor, which makes it possible to easily reproduce halftones and intermediate colors in a still image in a pseudo manner.

(Prior Art) In recent years, with the spread of semiconductor memory, it has become common practice to store images from pre-vision receivers, video tape recorders, video cameras, etc., and display them as still images on a television monitor or output them to a printer. ing. In addition to this, image processing and image analysis, such as enlarging, reducing, or extracting features of the stored image using a personal computer, etc., have been developed mainly in the field of industrial design.

However, if a still image is to be reproduced faithfully to the input video, for example, in the case of a color image consisting of red, green, and blue, a minimum of 4 to 8 bits for each color (16 to 256 colors) is required. It is said that a resolution of Since a large capacity memory is required to store such a large amount of video data, the price of memory as a whole becomes quite expensive even though the price of semiconductor memory is decreasing. Additionally, with this increase in memory capacity,
Another problem arises in that the scale of the peripheral circuitry increases.

On the other hand, in the fields of binarizing input video to obtain still images, such as photo transmission and facsimile, the so-called dither method is well known as a means of obtaining still images. In this method, a video signal obtained from an original image is input to a comparator whose threshold level is varied stepwise to obtain a plurality of binarized images with different gradations.

These images are then appropriately combined to obtain a single still image with continuous gradations (a-light).

However, this method has the problem that a circuit for varying the threshold value is required, which complicates the device. Furthermore, the process for combining a plurality of binarized images as described above is complicated, and there is also the problem that it is difficult to perform this in real time.

(Object of the Invention) The present invention has been made in view of the above circumstances, and provides a still image video signal processing method and a still image video signal processing method that can faithfully reproduce human video with a relatively small memory capacity. Zuro aims to provide equipment.

Another object of the present invention is to express gradations of still images with a relatively simple configuration.

(Structure of the Invention) In order to achieve such an object, the present invention superimposes a clock pulse near the average level of a video signal of a still image, and makes this clock pulse superimposed video signal have a period shorter than the period of the clock pulse. The main feature of this method is to obtain a still image video signal to be provided to an external display device based on sampling at a short timing.

(Example) Hereinafter, an example of the still image video signal processing method according to the present invention will be described.

FIG. 1 is an explanatory diagram of the embodiment.

Figure (a) is a video signal of a still image, and the chain line A in the figure
indicates the average level of this video signal. A clock pulse is superimposed near the average level of such a video signal, as shown in FIG. Then, when the video signal with the clock pulses superimposed in this way is manually applied to a switching element having a threshold level approximately equal to the average value level, it is possible to obtain a binary signal as shown in FIG. can.

FIG. 4B shows a binary signal obtained when a video signal without superimposing a clock pulse is input to the same switching element as described above. As can be seen from the figure, the portion of the video signal with a level higher than the threshold level becomes a bright portion, and the portion with a lower level becomes a dark portion. On the other hand, in the case of FIG. 2D in which clock pulses are superimposed, a fine repeating portion of bright portions and dark portions, that is, a halftone portion occurs between the bright portion and the dark portion.

For example, when a still image is displayed in black and white, the halftone portion is displayed in gray. Further, when the input video signal is a red color signal, the halftone portion has fine repetitions of red and black, and therefore this halftone portion has a brown color which is an intermediate color between red and black. It goes without saying that such a halftone portion is based on the clock pulse superimposed on the video signal as described above.

Therefore, it is necessary to sample the binarized signal shown in FIG. 3(d) at a timing shorter than the period of the superimposed clock pulse and store it in a memory with a storage capacity for one screen, for example. For example, a halftone binary signal can be extracted at any time if necessary.

FIG. 2 is an explanatory diagram of another embodiment of the method of the present invention.

In this embodiment, a video signal in which a clock pulse is superimposed on an average level, as shown in FIG. 2(a), is A/D converted into a 3-bit digital signal. The figure (b) is
It shows an A/D converted digital signal. The same figure (c
) indicates a signal obtained by further D/A converting the A/D converted signal. On the other hand, FIG. 3 shows a case where a video signal without superimposing a clock pulse is A/D converted.

As can be seen by comparing Figure 2 (C) and Figure 3 (C),
The component resulting from the superimposition of the clock pulse fills in the differences between the gradations of the video signal, thereby displaying intermediate tones and intermediate colors. Therefore, when displaying a still image, it is possible to reproduce an image closer to the original image by superimposing clock pulses.

In other words, it is equivalent to increasing the resolution in the overlapped portion of the clock pulses. Normally, to increase the resolution, it is necessary to increase the number of bits of the A/D converter.
According to this invention, the halftones and intermediate colors of the original image can be reproduced without particularly increasing the number of bits of the A/D converter.

Next, an embodiment of the still image video signal processing device according to the second invention will be described.

FIG. 4 is a block diagram showing an outline of the configuration of the embodiment,
FIG. 5 is a specific circuit diagram of the pseudo gradation generation circuit 10 shown in FIG. 4.

A luminance signal as a video signal of a still image is given to a pseudo gradation generation circuit IO. This pseudo gradation generation circuit IO is
As shown in FIG. 5, it includes an NPN switching transistor TRI having a threshold level approximately equal to the average level of the luminance signal of a still image. A resistor R1 and a speed-up capacitor CI are connected in parallel to the base of the transistor TRI. Further, a diode DI for improving rise is connected in the forward direction from the base to the collector of the transistor TRI. Further, the base is grounded via a resistor R2. The collector of the transistor TRI is connected to the DC voltage line 10B via a resistor R3, and the emitter is grounded. Furthermore, a clock pulse generation circuit 11 is connected to the base of the transistor TRI via a DC element capacitor C2 and a resistor R4 connected in series.

This clock pulse generation circuit 11 generates a 3 MHz clock pulse. Furthermore, a vertical drive signal is applied to this clock pulse generation circuit 11, so that the oscillation state of this circuit is locked to the vertical drive (signal).

There is.

The output signal of the pseudo gradation generating circuit 10 as described above is applied to the memory 20. This memory 20 is controlled by a control section 30. The stored contents of the memory 20 are taken out as video data via the signal conversion circuit 40 and provided to an external display device (not shown).

Next, the operation of the above-described embodiment will be explained.

For example, suppose that the luminance signal of a still image as shown in FIG. 1(a) is applied to the base of the transistor TRI.

On the other hand, the 3 output from the clock pulse generation circuit 11
A MHz clock pulse is applied to the base of transistor TRI via resistor R4 and capacitor C2. Since the DC component of the clock pulse is blocked by the action of the capacitor C2, the level of the clock pulse superimposed on the luminance signal will eventually change depending on the level of the luminance signal. That is, at the average level of the luminance signal, the amplitude of the superimposed clock pulse is large, and at low and high levels of the luminance signal, the amplitude of the clock pulse is small (see FIG. 1(C)).

Since the transistor 'I'RI has a Threnjord level that is approximately equal to the average level of the luminance signal, the binary signal of the luminance signal, which is the output of the transistor TRI, is as shown in FIG. 1(d). As shown, the result is a signal with halftone parts.

This binarized signal is given to memory 20. memory 20
is controlled by the control unit 30 to sample the binarized signal at a timing shorter than the period of the clock pulse superimposed on the luminance signal (in this embodiment, 28.636 MHz), and sample the binarized signal for one screen. Store the luminance signal. The contents stored in the memory 20 are subjected to Norial/Parallel conversion by the signal conversion circuit 40 based on a control signal from the control unit 30, and then output as video data to an external display device (not shown), such as a personal computer. . As a result, a still image with halftones is displayed on the CRT screen of the personal computer. At this time, as mentioned above, the clock pulse superimposed on the luminance signal is synchronized with the vertical drive signal, so even if a difference beat component occurs between the luminance signal and the clock pulse, the beat is Ingredients have stopped. Therefore, the unpleasant phenomenon in which the striped pattern based on the beat component moves around on the CRT screen is avoided.

In addition, although the above-mentioned embodiment was explained by taking as an example the case where the luminance signal is binarized, the present invention is not limited to this, and R,
It can also be applied to the case of binarizing G and H color signals.

Next, an embodiment of a still image video signal processing device according to the third invention will be described.

FIG. 6 is a block diagram schematically showing the configuration of the embodiment;
FIG. 7 is a circuit diagram showing a specific configuration of the pseudo intermediate color generating circuit 70 in the embodiment shown in FIG.

The video signal is provided to a decoder 50 and a synchronization separation circuit 60. The decoder 50 receives a clamp pulse from the sync separation circuit 60. The decoder 50 supplies primary color signals R and G to a pseudo intermediate color generation circuit 70.

Give B. The pseudo intermediate color generation circuit 70 generates a signal R in which a clock pulse is superimposed near the average value level of the color signal.
°, Go, B” is output.

This pseudo-intermediate color generation circuit 70 includes three DC amplifier circuits 71, 72, and 73 that manually generate each color signal as shown in FIG.
including. Each DC amplifier circuit includes a PNP type transistor TR2 that inputs each color signal individually. The emitter of this transistor TR2 is connected to the power supply line 10B via a parallel-connected resistor R5 and capacitor C3.

Further, its collector is grounded via a resistor R6, and is also connected to the base of an NPN type transistor TR3 in the next stage. The collector of the transistor TR3 is connected to the power supply line 1,000B via a resistor R7.

Further, its emitter is grounded via a resistor R4. Further, the base of the transistor TR3 is connected to a clock pulse generation circuit 74 via a DC blocking capacitor C4 and a resistor R9 connected in series. A vertical drive signal is input to this clock pulse generation circuit 74. The clock pulse generation circuit 74 outputs a 3 MHz clock pulse synchronized with the vertical drive signal. Further, the output terminal of the clock pulse generation circuit is grounded via a variable resistor VR.

The signal R1G'' output from the pseudo intermediate color generation circuit 70,
Bo is individually given to A/D converters 81, 82, and 83. Each A/D converter is a 3-bit converter, and its output signal is individually given to memories 91, 92, and 93, respectively. Since each memory inputs a 3-bit signal manually, three image memories each having eight memories for one screen are provided in the depth direction. The output of each memory is D/A
Transducers 101, 102, and 103 are each provided individually. The output of each D/A converter is then given to an external display (not shown), such as a monitor television.

Note that the A/D converter 81, 82, 83, memory 91
, 92.93 and D/A converter 101゜102.103
is controlled by a control section 110 which is supplied with horizontal and vertical synchronization pulses from a synchronization separation circuit 60.

Next, the operation of the above-described embodiment will be explained with reference to FIG.

The decoder 50 that manually inputs the video signal has a synchronization separation circuit 60.
When a clamp pulse is applied from the output terminal, color signals R, G, and B, in which DC components are reproduced, are output. These color signals are sent to the DC amplification circuit 71 of the pseudo intermediate color generation circuit 70,
72.73 are given separately. Figure 8(a)
exemplarily shows the R signal St given to the DC amplifier circuit 71.

On the other hand, by inputting the vertical drive signal S5 as shown in FIG. 8(e), the clock pulse generation circuit 74 outputs a clock pulse S4 locked to the signal S5 as shown in FIG. 8(d). . This clock pulse S4 is input to the base of the transistor TR3, with direct current being blocked by the action of the capacitor C4. therefore,
A signal S2 as shown in FIG. 8(b) is input to the base of the transistor TR3. This signal S2 is inverted and amplified by the transistor TR3, so that the clock pulses are superimposed near the average level of the input color signals R', Go, and B, as shown in FIG. 8(C).

A signal S3 is output.

Note that if the amplitude of the superimposed clock pulse is too large,
If the black level is raised or the white level is lowered, the still image displayed on the monitor TV becomes grayish overall. Therefore, it is desirable to appropriately adjust the resistance value of the variable resistor VR provided at the output terminal of the clock pulse generation circuit 74 so that the clock pulse is superimposed only on the average level of the input color signal.

Each color signal R', Go, Bo on which a clock pulse is superimposed
are individually given to A/D converters 81, 82, and 83,
Each is converted into a 3-bit digital signal. The control unit 1 controls the sampling frequency at this time to be higher than the frequency (3MHz) of the superimposed clock pulse.
10. The sampling frequency in this example is set to 28.636 MHz.

Each color signal R1°G,'B° converted into a digital signal is individually provided to memories 91, 92, and 93, respectively. The three bits constituting the color signal are stored in three corresponding memory areas 91a, 91b,
91c, ... are stored.

The color signal stored in this way is read out by a control signal from the control unit 11O, and is sent to the D/A converter 101.
．． 102 and 103 respectively converted to analog signals,
It is output to a television monitor (not shown).

(Effects of the Invention) As described above, in the still image video signal processing method according to the present invention, a clock pulse is superimposed near the average level of a still image video signal, and this clock pulse superimposed video signal is Since a video signal of a still image is provided to an external display device based on sampling at a timing shorter than the pulse period, halftones and intermediate colors of the original image can be easily reproduced.

The still image video signal processing device according to the second invention is composed of a switching transistor and the like that superimposes a clock pulse near the average level of a video signal and binarizes the clock pulse, and is a device that is configured with a switching transistor or the like that superimposes a clock pulse near the average level of a video signal and binarizes the clock pulse. Since there is no need to vary the switching transmissive threshold as in the case of the conventional method, it is possible to realize a device capable of reproducing the intermediate tones and intermediate colors of the original image with a relatively simple configuration.

Further, according to the present invention, as in the case of the dither method,
Since there is no need to perform processing to combine multiple binarized images, it is possible to output video signals of still images in real time.

A video signal processing device for a still image according to a third aspect of the present invention performs DC amplification by superimposing a clock pulse near the average level of a video signal of a still image, and transmits the amplified signal at a timing shorter than the period of the clock pulse. It samples the signal, converts it to a digital signal, and stores it in a storage device. That is, since this invention equivalently improves the resolution of that part by superimposing clock pulses, it is necessary to increase the number of pits in the A/D converter and increase the memory capacity accordingly in order to increase the resolution. There's no need.

Therefore, according to the present invention, halftones and halftones of the original image can be reproduced with a relatively small memory capacity.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of an embodiment of the method of the present invention, FIG. 2 is an explanatory diagram of another embodiment of the method of the present invention, and FIG. 3 is a clock pulse applied to a video signal used for comparison with the aforementioned embodiment. FIG. 4 is a block diagram schematically showing the configuration of the signal processing device according to the second invention, and FIG. 5 is a detailed diagram of the fco pseudo gradation generation circuit shown in FIG. 6 is a block diagram schematically showing the configuration of a signal processing device according to the third invention, FIG. 7 is a specific configuration diagram of the pseudo intermediate color generation circuit shown in FIG. 6, and FIG. 8 is an operational waveform diagram of the circuit shown in FIG. 7. FIG. IO...Pseudo gradation generation circuit, 11...Clock pulse generation circuit, 20...Memory, 30...Control unit, 70
. . . Pseudo intermediate color generation circuit, 74 . . Clock pulse generation circuit, 81 to 83 . . . A/D converter, 91 to 93.
-Memory, 101-103...D/A converter.

Claims (3)

[Claims] (1) A clock pulse is superimposed near the average level of a video signal of a still image, and this clock pulse superimposed video signal is provided to an external display device based on sampling at a timing shorter than the period of the clock pulse. A still image video signal processing method characterized by obtaining a still image video signal. (2) a switching transistor that has a threshold level approximately equal to the average level of a video signal of a still image and that has a base terminal supplied with the video signal and a clock pulse whose direct current is blocked; and an output signal of the switching transistor. , a stationary device characterized by comprising a storage means for sampling at a timing shorter than the period of the clock pulse and storing it, and a control means for transferring the contents stored in the storage means to an external display device. Image video signal processing device. (3) a DC amplification circuit that inputs a video signal of a still image and a clock pulse in which DC is blocked, and superimposes the clock pulse near the average level of the video signal; an A/D converter that samples an output signal at a timing shorter than the period of the clock pulse and converts it into a digital signal; a storage means that stores the output signal of the A/D converter; 1. A still image video signal processing device comprising: a D/A converter that converts a digital video signal into an analog signal and outputs the analog signal to an external display device.