JPS621179U

JPS621179U -

Info

Publication number: JPS621179U
Application number: JP9320585U
Authority: JP
Priority date: 1985-06-20
Filing date: 1985-06-20
Publication date: 1987-01-07

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示す機能ブロツ
ク図、第２図は従来の進行処理装置を示す機能ブ
ロツク図、第３図は目標からの反射光が４象現検
出器に受光された時の図、第４図Ａは第１図にお
ける４象限検出器１の出力信号図、第４図Ｂは第
１図における増幅器６の出力信号図、第４図Ｃは
第１図における増幅器６の出力信号を各チヤンネ
ルに導入した時の各チヤンネルの信号図、第４図
Ｄは第１図におけるゲート回路７の出力信号図で
ある。図中において、１は４象限検出器、２，３，４
は遅延回路、５は電流／電圧変換増幅器、６は増
幅器、７はゲート回路、８は演算回路、９は４象
限検出器１に目標からの反射光を受光した状態を
示す。なお、各図中同一符号は同一または相当部
分を示す。 Fig. 1 is a functional block diagram showing an embodiment of this invention, Fig. 2 is a functional block diagram showing a conventional progress processing device, and Fig. 3 shows a system in which reflected light from a target is received by a four-quadrant detector. FIG. 4A is an output signal diagram of the four-quadrant detector 1 in FIG. 1, FIG. 4B is an output signal diagram of the amplifier 6 in FIG. 1, and FIG. 4C is a diagram of the output signal of the amplifier 6 in FIG. FIG. 4D is an output signal diagram of the gate circuit 7 in FIG. 1. In the figure, 1 is a 4-quadrant detector, 2, 3, 4
5 is a delay circuit, 5 is a current/voltage conversion amplifier, 6 is an amplifier, 7 is a gate circuit, 8 is an arithmetic circuit, and 9 indicates a state in which the four-quadrant detector 1 receives reflected light from a target. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

A four-quadrant detector that receives reflected light from a target and converts it into a current, multiple delay circuits that each give a corresponding delay to the four-channel signal system from this four-quadrant detector, and an output current of the delay circuit. A current/voltage conversion amplifier that converts and amplifies current/voltage, an amplifier that amplifies the output of this amplifier, a plurality of delay circuits that delay the output signal of this amplifier, a gate circuit that extracts the desired signal, and this gate. A signal processing device comprising: an arithmetic circuit that calculates a guidance error signal with respect to a target from an output of the circuit.