JPS62117844U - - Google Patents

Info

Publication number
JPS62117844U
JPS62117844U JP529386U JP529386U JPS62117844U JP S62117844 U JPS62117844 U JP S62117844U JP 529386 U JP529386 U JP 529386U JP 529386 U JP529386 U JP 529386U JP S62117844 U JPS62117844 U JP S62117844U
Authority
JP
Japan
Prior art keywords
solid
terminal
count value
state timer
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP529386U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP529386U priority Critical patent/JPS62117844U/ja
Publication of JPS62117844U publication Critical patent/JPS62117844U/ja
Pending legal-status Critical Current

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Landscapes

  • Measurement Of Predetermined Time Intervals (AREA)
  • Electronic Switches (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面はこの考案の一実施例を示し、第1図はソ
リツドステートタイマの実装前の斜視図、第2図
は第1図に対応するタイマ回路図、第3図はソリ
ツドステートタイマの実装後の斜視図、第4図は
第3図に対応するタイマ回路図である。 1…ソリツドステートタイマ、3…入力端子、
4…電源端子、5…出力端子、6…0ボルト端子
、7,9…不使用の端子、8…使用端子、14…
プリント基板、15…導電パターン。
The drawings show an embodiment of this invention, in which Fig. 1 is a perspective view of the solid-state timer before implementation, Fig. 2 is a timer circuit diagram corresponding to Fig. 1, and Fig. 3 is the implementation of the solid-state timer. The later perspective view, FIG. 4, is a timer circuit diagram corresponding to FIG. 3. 1...Solid state timer, 3...Input terminal,
4...Power terminal, 5...Output terminal, 6...0 volt terminal, 7, 9...Unused terminal, 8...Used terminal, 14...
Printed circuit board, 15...conductive pattern.

Claims (1)

【実用新案登録請求の範囲】 複数の計数値選択用端子と、共通端子とを備え
、計数機能を有するソリツドステートタイマであ
つて、 時間設定に対応して不使用の端子が切断された
任意数の使用計数値選択用端子のみを、基板上の
導電パターンに接続した ソリツドステートタイマ。
[Claims for Utility Model Registration] A solid-state timer that is equipped with a plurality of count value selection terminals and a common terminal, and has a counting function, wherein the unused terminals are disconnected in accordance with the time setting. A solid-state timer in which only the terminal for selecting the count value used is connected to the conductive pattern on the board.
JP529386U 1986-01-18 1986-01-18 Pending JPS62117844U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP529386U JPS62117844U (en) 1986-01-18 1986-01-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP529386U JPS62117844U (en) 1986-01-18 1986-01-18

Publications (1)

Publication Number Publication Date
JPS62117844U true JPS62117844U (en) 1987-07-27

Family

ID=30786739

Family Applications (1)

Application Number Title Priority Date Filing Date
JP529386U Pending JPS62117844U (en) 1986-01-18 1986-01-18

Country Status (1)

Country Link
JP (1) JPS62117844U (en)

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