JPS6211758B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is an apparatus that can thin the binary pattern so that there is no distortion near the intersection, even when character parts intersect when performing character recognition. It is related to.

One of the leading methods in optical character recognition is a recognition method in which characters to be recognized are made into thin lines and attention is paid to character lines, end points, branch points, intersections, etc., and this method has achieved considerable success. The conditions that cannot be met in line thinning processing used in conventional character recognition are (i) ``maintaining the continuity of the black dot area, and (ii) ``setting the line width to 1''; ), it would be possible to achieve the desired performance by covering patterns with somewhat poor quality using the recognition method. Guarantees for 4-connection and 8-connection are located next to the above items. The thinning processes proposed so far are mainly 3×
Parallel processing divided into 2-cycle or 4-cycle subcycles to maintain connectivity using a mask of 3 [For example, Tamura, Mori, "Parallel thinning algorithm for binary figures", 1972. IEICE National Conference. There are many conference papers No. 1539 (the table of contents shows 12-3 Information and Control C Division No. 1359, but No. 1539 is incorrect)]. The above method has already been put into practical use because the number of tables to be prepared is of a realizable quantity and the circuit can be realized relatively easily by a combination of logic elements. However, since there is only information about the adjacent mesh in the vertical, horizontal, diagonal, and diagonal directions, and it is divided into subcycles to maintain connectivity, there is no problem in thinning a single stroke, but thick strokes may intersect. Distortion may occur where the intersection point is crossed, and the output at the intersection may be undesirable. Figure 1 b-1 and b-2 are examples of this, where b-1 is the original pattern and is a criss-cross of strokes with a line width of 5, starting from the bottom and right side in the first cycle, and in the second cycle. When a line thinning method consisting of two cycles in which one bit is removed from each of the upper and left sides is executed, an output pattern with a line width of 1 as shown in FIG. 1b-2 is obtained. 1 in the original pattern,
The number 2 means the mesh that is removed the first time and the mesh that is removed the second time. The expected output pattern from the original pattern is a symmetrical pattern in which the strokes with a line width of 1 cross each other, as shown in Figure 1 a-2, but since it is divided into subcycles, it is ) Asymmetric intersection〓〓〓〓〓
A distorted pattern is obtained near the difference point. Although it is possible to cover this degree of distortion with the recognition method, it is possible to cover more complicated patterns, such as the second one.
For the original pattern as shown in Figure b-1, a distorted pattern as shown in Figure b-2 is output. Figure 2 a-
Compared to pattern 2, it is quite difficult to cover this on the recognition method side.

The purpose of the present invention is to perform character recognition in Figure 1 a-1, a.
-2. It is an object of the present invention to provide an apparatus having a simple configuration that outputs a high quality thinning pattern having intersections without distortion as shown in FIG. 2 a-1 and a-2.

Next, the present invention will be explained in detail using figures.

FIG. 3 is a block diagram showing one embodiment of the present invention. Input pattern quantization unit 1 (hereinafter referred to as quantization unit 1)
) scans an input pattern in a two-dimensional array, converts the shading at each quantized pattern position into a binary value, and outputs it.
This is the scanning mechanism used for this purpose, and its details will be omitted. A signal 11 is its output and becomes an input to the thinning section 2. The line thinning unit 2 thins the input pattern until the line width becomes 1 or 2 bits, and sends the result as a signal 12 to the final line thinning unit 3 (hereinafter abbreviated as line thinning unit 3). Thinning section 3
This is a known wire thinning device for cutting a portion with a wire width of “2” to a wire width of “1”, and its details will be omitted. Further, a signal 52 is a control signal from the thinning section 2 to the control section 5, which will be described later, and a signal 51 is a control signal from the control section 5, which controls the operations of the quantization section 1, the thinning section 2, and the thinning section 3. Do the following. When the final thinning is completed, it is output as a signal 13 to a known pattern recognition device (not shown).

Next, the principle of the thinning section 2, which is the main part of the present invention, will be explained with reference to the drawings. Figure 4a shows the thinning section 2.
Temporary input pattern plane X ⁽¹⁾ Internal pattern plane ^{X that} temporarily stores internal patterns that will never be deleted during thinning ^{processing 2)} ) and
Skeletal pattern plane X that stores the skeleton pattern ⁽³⁾
(hereinafter abbreviated as plane X ⁽³⁾ ) and temporary output pattern plane X ⁽⁴⁾ , 6A is plane X ⁽¹⁾ , 71A
is plane X ⁽²⁾ , 72A is plane X ⁽³⁾ , 8A is plane X
⁽⁴⁾ is shown. Figure 4b shows each plane x ^(k) (k=
1, 2, 3, 4) is an example of a diagram logically explaining cell X, which takes binary values of 0 (white) and 1 (black).
^(k) Consists of _i , _j (i=1 to M, j=1 to N). still,
Temporary input pattern plane X ⁽¹⁾ Outermost x ⁽¹⁾ ₁ , _j (j
=
1~N), X ⁽¹⁾ _M , _j (j=1~N), X ⁽¹⁾ _i
, ₁ (i=1
~M), X ⁽¹⁾ _i , _N (i=1~M) are all set to 0.

The thinning algorithm is a method of deleting one bit at a time in one cycle so as not to lose connectivity from the periphery of the pattern. If we focus on just one cycle, it is surrounded by black bits on the top, bottom, left and right, and if it is also black bits, these are called internal patterns, and are not subject to deletion, but only if the above conditions are met. Bit is not satisfied. Among the bits that can be deleted, there are some that cannot be deleted in order to maintain continuity, and these are called skeletal patterns. Of the bits of the original pattern that do not correspond to the internal pattern or skeleton pattern, the bits that satisfy the deletion conditions are deleted. The above processing is performed during one cycle. Cell x ⁽²⁾ _i , _j is determined as follows. Note that ∧ indicates logical product, and ∨ indicates logical sum.

x ⁽²⁾ _i , _j = x ⁽¹⁾ _i , _j ∧x ⁽¹⁾ _i-1 , _j ∧x ⁽¹⁾ _i , _j-1 ∧x ⁽¹⁾ _i , _j+1 ∧x ^(1
) _i+1 , _j (1) That is, cell x ⁽²⁾ _i , _j is black, and cell x ⁽¹⁾ _i , _j is black, and
The four neighboring points on the top, bottom, left and right are black dots, and are not subject to deletion during 1-bit thinning. Next, cell x ⁽³⁾ _i , _j
is determined as follows.

x ⁽³⁾ _i , _j = x ⁽¹⁾ _i , _j ∧x ⁽²⁾ _i , _j ∧(x _i , _j ) (2) where (x _i , _j )= ₁ (x _i , _j ) ∨ ₂ (x _i , _j ) (2-0) ₁ (x _i , _j )=x ⁽²⁾ _i-1 , _j ∧x ⁽²⁾ _i , _j-1 ∧x ⁽²⁾ _i , _j+1 ∧x ^{(2 )} _i+1 , _j (2
-1) ₂ (x _i , _j ) = (x ⁽¹⁾ _i-1 , _j-1 ∧x ⁽¹⁾ _i-1 , _j ∧x ⁽¹⁾ _i , _j-1 )∨(x ⁽¹⁾ _i-
1 , _j+1 ∧x ⁽¹⁾ _i-1 , _j ∧x ⁽¹⁾ _i , _j+1 ) ∨(x ⁽¹⁾ _i+1 , _j-1 ∧x ⁽¹⁾ _i , _j-1 ∧x ⁽¹⁾ _i+1 , _j )∨(x ⁽¹⁾ _i+1 , _j+1 ∧x
⁽¹⁾ _i , _j+1 ∧x ⁽¹⁾ _i+1 , _j ) (2-2) 〓〓〓〓〓
In other words, the cell x ⁽³⁾ _i , _j is not an internal pattern in the black part (x ⁽²⁾ _i , _j = 0) and is not adjacent to the internal pattern in any of the upper, lower, left, or right directions, or is the fourth cell on the storage section 6A. This part satisfies the mask shown in Figure c, and should not be deleted to ensure connectivity even after thinning. Finally, the cells x ⁽⁴⁾ _i and _j are determined to satisfy the deletion conditions (i) and (iii) of FIG. 4e among the bits that can be deleted, and the masks in which their directions are changed respectively.

x ⁽⁴⁾ _i , _j = {x ⁽¹⁾ _i , _j ∧x ⁽²⁾ _i , _j ∧x ⁽³⁾ _i , _j ∧g(x _i , _j )}∧x ⁽¹⁾ _i , _j ( 3
) However, g(x _i , _j )=g ₁ (x _i , _j )∨g ₂ (x _i , _j ) g ₁ (x _i , _j )=(x ⁽²⁾ _i+1 , _j ∧x ⁽¹⁾ _{i -1} , _j )∨(x ⁽²⁾ _i , _j+1 ∧x ⁽¹⁾ _i , _j-1
) ∨(x ⁽²⁾ _i , _j-1 ∧x ⁽¹⁾ _i , _j+1 )∨(x ⁽²⁾ _i-1 , _j ∧x ⁽¹⁾ _i+1 , _j )(3-1) g ₂ (x _i , _j ) = (x ⁽²⁾ _i-1 , _j-1 ∧x ⁽¹⁾ _i , _j+1 ∧(x ⁽¹⁾ _i+1 , _j ∧x ⁽¹⁾ _i+1 ,
_j+1 ) ∨(x ⁽²⁾ _i-1 , _j+1 ∧x ⁽¹⁾ _i , _j-1 ∧x ⁽¹⁾ _i+1 , _j-1 ∧x ⁽¹⁾ _i+1 , _j ) ∨(x ⁽²⁾ _i+1 , _j−1 ∧x ⁽¹⁾ _i−1 , _j ∧x ⁽¹⁾ _i , _j+1 ∧x ⁽¹⁾ _i+1 , _j ) ∨(x ⁽²⁾ _i+1 , _j+1 ∧x ⁽¹⁾ _i−1 , _{j− 1} ∧x ⁽¹⁾ _i-1 , _j ∧x ⁽¹⁾ _i , _j-1 ) (3-
2) This formula satisfies the mask in Figure 4d for the cell x ⁽¹⁾ _i ,
_j
(black) indicates that the output will be temporarily output. In Figure 4 d, 0 is the point corresponding to the white point, 1 is the point corresponding to the black point, and is the point where x ⁽¹⁾ _i , _j = 1, □
1 represents the point x ⁽²⁾ _i , _j = 1 or x ⁽¹⁾ _i , _j = 1, and in addition to this, the direction is changed and three types of masks are considered. It can be guaranteed that equation (4) changes the point from 1 to 0 that satisfies only the mask in FIG. 4d and the other three masks with different directions as follows.

Consider points that satisfy (i) in Figure 4e. The four concatenated adjacent bits of is 1 from equation (1). Therefore, by assigning 0 and 1 to the remaining 4 bits, the total becomes
There are 16 ways, and 7 of them satisfy Figure 4 (ii). The remaining nine patterns are the upper nine in FIG. 4d. Bits that are not 4 concatenated adjacent to 0 are 1, so they are represented by □1.

Similarly, consider points that satisfy (iii) in Fig. 4e.
As mentioned earlier, the number of 4-connected adjacent bits is 1, so a pattern like that shown in FIG. 4e (iv) is impossible. Assigning 0 and 1 to the remaining 2 bits results in a total of 4 ways, all of which are shown in 4 below in Figure 4d.
It is individual. 0 and 4 concatenated non-adjacent bits are 1
Therefore, it is represented by □1.

That is, from the definition of x ⁽²⁾ _i , _j = 1, it is clear that connectivity is guaranteed even if x ⁽¹⁾ _i , _j that satisfies Fig. 4d is deleted.

Looking at equations (1), (2), and (3), the subscripts of x ^(k) are all i±l, j±l (l=-1, 0, 1), so at first glance it looks like 3 It looks like the processing is being performed in a ×3 area, but if equations (2) and (3) are all represented by x ⁽¹⁾ _n , _o , the processing is actually being performed in a 5 × 5 area. I know that there is. It is natural that line thinning can be performed with higher precision if the decision to delete line thinning is made in a 5 x 5 area than in a 3 x 3 area, but in terms of feasibility, it has been Line thinning processing has been carried out in the area of . In other words, logically, in a 3 x 3 area, a maximum of 2 ^{to 9} states can be prepared, which makes it possible to realize a logic circuit configuration, but in a 5 x 5 area, the maximum number of states is 2 to ²⁵ , and all This is because it is difficult to construct a logic circuit by preparing states. Therefore, a logic design for a 5×5 area that can be easily realized is required. The principle of the present invention is to essentially design the logic of a 5x5 area by combining multi-layered 3x3 areas, and can be realized with a simple configuration.

A first embodiment in which the line thinning section 2 is incorporated into a device will be described below with reference to the drawings.

FIG. 5 is a block diagram showing an example of the line thinning section 2, which consists of a pattern storage section 6 and a logic circuit group 7.
Storage unit 6 stores planes X ⁽¹⁾ and X ⁽⁴⁾ in the logical explanation.
The logic circuit group 7 plays the role of planes X ⁽²⁾ , X ^(
3) and a group of logic circuits that realize each equation (1), (2), and (3).

FIG. 6 is a configuration diagram showing an example of the storage section 6. As shown in FIG.
As shown in the figure, the storage unit 6 has MXN shift registers 61 connected in series in an array corresponding to pattern scanning, and input signals are output from the quantization unit 1 by a control signal 51 shown in FIG. The signal 11 is determined, and the clock 61i shown in FIG. 6 moves in the direction of the arrow.
Serial shift. The shift register has 1 bit of information and receives an input signal 61s, a clock 61i,
The output signal 61t is determined by the load signal 61j and the load input signal 76t. The load input signal 76t is a thinning output signal to be described later, and its negative signal is
It is also supplied to the AND gate 82, while the signal 61t
is also supplied to the AND gate 82, and this output signal 8
2t becomes the thinning end detection signal, and the OR gate 8
10. The output 810t becomes a thinning completion detection signal for the entire pattern.

FIG. 7 shows the shift register 61 of the storage section 6 and eight adjacent shift registers 61a, 61b, 61.
7 is a configuration diagram showing an example of converting the outputs of the circuits c, 61d, 61e, 61f, 61g, and 61h into inputs to the logic circuit group 7. FIG. The output signal 61t of the shift register 61 and the four connected adjacent shift registers 61 on the upper, lower, left and right sides
b, 61d, 61e, 61g output signal 61bt,
61dt (=61s), 61et, and 61gt each serve as input signals to the logic circuit group 7. Formula (2
-2) Shift register 61 as an input corresponding to
output signal 61at of a and shift registers 61b, 6
The negation signals of the output signals 61bt and 61dt of 1d are
AND gate 62 and shift register 6
1c output signal 61ct and shift register 61b,
The output signal 61bt of 61e and the negation signal of 61et are
It is supplied to the AND gate 63 and the shift register 6
1ft and the negative signals of the output signals 61dt and 61gt of the shift registers 61d and 61g are supplied to the AND gate 64, and the output signal 61 of the shift register 61h is supplied to the AND gate 64.
output signal 6 of gt and shift registers 61e and 61g
1et, 61gt are supplied to the AND gate 65, and the respective AND signals 62t, 63t, 64t, 6
5t are input signals to the logic circuit group 7, respectively. Then, as the signals required in (3-2), the negative signals of the output signals 61at, 61bt, and 61dt of the shift registers 61a, 61b, and 61d are ANDed.
Supplied to gate 66, shift registers 61b, 6
1c, 61e output signals 61bt, 61ct, 61et
is supplied to the AND gate 67, and output signals 61 of the shift registers 61d, 61f, 61g
AND gate 68 for negative signals of dt, 61ft, 61gt
and shift registers 61g, 61h, 61
Negation signals of output signals 61gt, 61ht, and 61et of e are supplied to an AND gate 69, and AND signals 66t, 67t, 68t, and 69t of each AND gate become input signals to the logic circuit group 7, respectively.

FIG. 8 is an example of a circuit corresponding to formula (1), which constitutes a part of the logic circuit group 7. Input signals 61bt, 61dt, 61t, 61et, 6 from storage unit 6
1gt corresponds to shift register 61 of storage unit 6
is supplied to the AND gate 71, and the AND signal 71t
issue. Other AND gates 71a, 71b,
71c, 71d, 71e, 71f, 71g, 71
h are shift registers 61a, 61b,
61c, 61d, 61e, 61f, 61g, 61
h. Formula (2-1)
AND gates 71b, 71 as applicable to
Output signals 71bt, 71dt of d, 71e, 71g,
The negative signals of 71let and 71lgt are the AND gate circuit 7
10 and outputs an AND signal 710t, which becomes an input to the next layer.

FIG. 9 is an example of a circuit corresponding to formula (2), and constitutes a part of the logic circuit group 7. signal 710t,
62t, 63t, 64t, 65t are OR gate 7
3, outputs the OR signal 73t, and the signal 7
A negative signal of 3t, 61t and a signal 71t is supplied to an AND gate 72 to output a signal 72t. other OR
The gate and AND gate are stored in the memory section 6 as in FIG.
shift registers 61a, 61b, 61c, 61
d, 61e, 61f, 61g, and 61h, respectively.

FIG. 10a is an example of a circuit corresponding to equations (3-1) and (3-2), and constitutes a part of the logic circuit group 7. Supplying the negative signal of the signal 61gt from the storage unit 6 and the signal 71bt to the AND gate 745,
The negation signal of the signal 61et and the signal 71dt are supplied to the AND gate 746, and the negation signal of the signal 61dt and the signal 71dt are supplied to the AND gate 746.
1et is supplied to the AND gate 747, the negative signal of the signal 61bt and the signal 71gt are supplied to the AND gate 748, and the respective signals 745t, 746t, 74
7t and 748t are supplied to the OR gate 7401. AND gate 7 of signal 66t and signal 71ht
41, the signal 67t and the signal 71ft to the AND gate 742, and the signal 68t and the signal 71ct to the AND gate 742.
The signal 69t and the signal 71at are supplied to the AND gate 744t, and the respective signals 741t, 742t, 743t, 744
t is supplied to OR gate 7402. Two OR games〓〓〓〓〓
Signal 7401 output from ports 7401, 7402
t, 7402t are supplied to the AND gate 74, and the AND signal is set as 74t. FIG. 10b is an example of a circuit corresponding to equations (3-1) and (3-2), which corresponds to FIGS. 8 and 9, and consists of the circuit shown in FIG. 10a.

FIG. 11 is an example of a circuit corresponding to formula (3),
It forms part of the logic circuit group 7. Input signal 61t and signal 74t from storage unit 6, and signal 71
The negative signals of t and 72t are supplied to the AND gate 75, and the negative signal of the signal 75t and the signal 61t are supplied to the AND gate 76, and the thinning output signal is set as 76t.

Next, the operation of the thinning section 2 will be explained.

The control unit 5 performs a storage operation by shifting the pattern obtained by the quantization unit 1 to the storage unit 6 as a signal 11, and starts thinning when the storage of the pattern is completed. In this embodiment, the shift is not performed during the thinning process in the thinning section 2. The output signal 76t of the logic circuit is determined by the output of each shift register 61, the end of line thinning is detected using the signal 76t and the signal 61t, and when the output signal 82t of the AND gate 82 is an ON signal, the line thinning process is started. Show what is being done. Therefore OR gate 8
When at least one of the signals supplied to OR gate 10 is an ON signal, the signal 810t becomes an ON signal and continues the thinning process, and when all the signals supplied to the OR gate are OFF signals, the input pattern and output Signal 810 when the pattern matches
t becomes an OFF signal, and the end of the thinning process is detected. When the control unit 5 detects the end of the line thinning process, the control unit 5 sequentially sends the line thinning unit 3 as a signal 12 while shifting the thinned pattern stored in the storage unit 6.
send to.

If the line thinning process is to be continued, the load input signal 76t is loaded into the shift register 61 by the load signal 61j, and the line thinning process is continued.

Note that the storage unit 6 is a shift register instead of a shift register.
A similar device can also be configured by rewriting PAM.

Next, a second embodiment in which the wire thinning section 2 is incorporated into a device will be described.

In the previous embodiment, patterns were processed in parallel (planarly) by connecting all the shift registers with the logic circuit group 7.

The embodiment described below requires a longer processing time than the former in that the pattern is processed one mesh at a time, but has the advantage that it requires fewer logic elements.

This will be explained below using figures.

FIG. 12 is a block diagram showing a second embodiment of the thinning section 2. In FIG. The binary pattern is serially shifted and input as a signal 11 to the pattern extraction section 6X. The input pattern is converted by the circuit section 7X, and the thinned pattern is stored in the storage section 8X.
Output by serial shift to . Since the size of the input pattern is fixed, the control unit 5 starts counting when the signal 11 is input to the extraction unit 6X, and can know the end of the 1-bit thinning process for the entire pattern. Send signal 52. signal 80
_xt is the output signal.

FIG. 13 is a configuration diagram showing an example of the extraction section 6X. The extraction unit 6X has a shift register 61 as shown in the figure.
Although X is connected in series in an array corresponding to pattern scanning, four rows may be used as shown in the figure. The input signal 60 is controlled by the control signal 51 from the control section.
Xs is determined to be either signal 11 or 80Xt, and serially shifted using clock signal 60Xi. The control unit starts counting at the same time as the input. Pattern extraction starts when the first bit of the pattern to be shifted reaches the shift register 61Xh.

FIG. 14 corresponds to equation (1) in the circuit section 7X, and x
⁽²⁾ A configuration diagram showing an example of a pattern plane storing _i and _j . Signal 61Xat, 61 from extraction unit 6X
Xbt, 61Xt, 61Xct, 61Xdt are cell x in formula (1)
⁽¹⁾ _i , _j-1 , x ⁽¹⁾ _i-1 , _j , x ⁽¹⁾ _i ,
corresponding to the outputs of _j , x ⁽¹⁾ _i+1 , _j , x ⁽¹⁾ _i , _j+1 and supplied to the AND gate 710X;
The output is shifted to a shift register of 71Xa or less using a clock signal 60Xi. Incidentally, as shown in FIG. 14, the number of shift register rows may be three.
Xd, 71Xe, 71Xf, 71Xg, 71Xh are cells x ⁽²⁾ _i-1 , _j-1 , x ⁽²⁾ _i , _j-1 , x ^(2
) _i+1 , _j-1 , x ⁽²⁾ _i-1 , _j , x
⁽²⁾ _i+1 , _j , x ⁽²⁾ _i-1 , _j+1 , x ⁽²⁾
_i , _j+1 , x ⁽²⁾ _i+1 , _j+1 , and the shift register 71X corresponds to x ⁽²⁾ _i , _j .

FIG. 15 is a block diagram corresponding to equations (2) and (3) of the circuit section 7X. Signal 61Xet cell x
⁽¹⁾ Outputs of _i and _j , signals 61Xt, 61ct, 61ft, 6
1
〓〓〓〓〓
dt, 61Xgt, 61Xht, 61Xit, 61Xjt as cell x ⁽¹⁾ _i-1 , _j-1 , x ⁽¹⁾ _i , _j-1 , x ^(
1) _i+1 , _j-1 , x ⁽¹⁾ _i-1 , _j , x
⁽¹⁾ _i+1 , _j , x ⁽¹⁾ _i-1 , _j+1 , x ⁽¹⁾
_i , _j+1 , x ⁽¹⁾ _i+1 , _j+1 output,
Signal 71Xat, 71Xbt, 71Xct, 71Xdt, 7
1Xet, 71Xft, 71Xgt, 71Xht in cell x
⁽²⁾ _i-1 , _j-1 , x ⁽²⁾ _i , _j-1 , x ⁽²⁾
_i+1 , _j-1 , x ⁽²⁾ _i-1 , _j , x
⁽²⁾ _i+1 , _j , x ⁽²⁾ _i-1 , _j+1 , x ⁽²⁾
It is a diagram shown in correspondence with the outputs of _i , _j+1 , x ⁽²⁾ _i +1, _j+1 . Therefore, configuring the circuit 700X that performs the operations of equations (2) and (3) can be easily realized with reference to FIGS. 7, 8, 9, and 10 of the previous embodiment.

FIG. 16a is a configuration diagram showing an example of the storage section 8X. Shift register 81X corresponds to shift registers 61Xe and 71X, and the clock signal is serially shifted in the same cycle as that of storage section 6 as signal 60Xi. shift register 81x
After that, similar shift registers are connected in series, the register following shift register 81X is for delay, and shift register 82X to shift register 8
Up to 3X are connected in series in an arrangement compatible with pattern scanning, and serve as a pattern memory. Storage section 6
The input pattern is passed through the circuit section 7 and subjected to line thinning processing and serial shift one bit at a time.
The thinned pattern, that is, the one-bit thinned pattern, is generated on the storage section 8 and serially shifted by the clock signal 60Xi. Therefore, by installing a counter in the control unit 5 and counting the number of shifts, the thinned pattern is stored in the storage unit 8.
shift register 82X to shift register 83
It can be detected that the data is stored in X.
(The control unit 5 uses this detection and the information of the signal 810Xt to generate the pattern output signal 80Xt of the storage unit 8X.
It is determined whether to send the signal to the thinning section 3 or to input it again as the input signal 60Xs to the storage section 6X. ) FIG. 16b shows an example of a circuit for detecting the presence or absence of line thinning. Output signal 81Xt of shift register 81X and output signal 6 of shift register 61Xe
1Xet is supplied to the AND gate 810X and the signal 8
Put out 10Xt. Signal _810X1 becomes an OFF signal when signal 81Xt and signal 61Xet match,
When the signal 61Xet is an ON signal and the signal 81Xt is an OFF signal, that is, when one bit is deleted in the thinning process, it becomes an ON signal. These signals are sent as signals 52 to the control section 5, and when the 1-bit thinning of the entire input pattern is completed, the thinning process is repeated, or the thinning pattern signal 80Xt (Fig. 16a) is sent to the storage section again. This information is used to control whether to input the signal 60Xs to the line thinning unit 6X, or to terminate the processing in the line thinning unit 2 and send the signal 80Xt to the line thinning unit 3.

The operation of the thinning section 2 is as shown in the configuration.

Next, a third embodiment in which the thinning section 2 is incorporated into a device will be described. In the second embodiment, the pattern signal is configured to cyclically move between the extraction section 6X, the circuit section 7X, and the storage section 8X until the pattern is no longer deleted, and the determination as to whether or not deletion has been performed is controlled. The department had to deal with it.
Since the line thinning device is intended for use in character recognition, etc., it is unlikely that the line width of the input pattern will fluctuate that much, and will be at most 1/2 to 2 to 3 times the width. Therefore, the line thinning section 2 can be configured by taking into consideration the line width of the input pattern in advance, preparing a plurality of stages of extraction sections 6X and circuit sections 7X, and finally adding a storage section 8X. With this, the 16th
The circuit for detecting the presence or absence of line thinning shown in FIG. b becomes unnecessary, and the configuration of the control section 5 can be simplified. Also, continuity is guaranteed when thinning the line, so once the line width is 1 or 2, the extraction section will be
The output pattern is guaranteed even if it passes through 6X and circuit section 7X.

The embodiments of the present wire thinning device have been described above, and the thinning section 2
Regarding this, three examples were shown. As is clear from the explanation, since the processing at each point has no directionality, it is possible to obtain a high-quality thinning pattern without distortion near the branching point, which has a great effect in practical use.

[Brief explanation of the drawing]

In Figures 1 and 2, a-1 and b-1 are input patterns, and a-2 and b-2 are examples of thinning patterns, where a is the thinning process performed by this device and b is the thinning process performed by the conventional device. An example of line thinning processing is shown. FIG. 3 is a block diagram showing an embodiment of the wire thinning device of the present invention. FIG. 4a is a block diagram showing the logical configuration of the thinning section 2, FIG. 4b is a logical layout diagram of the storage section 6A, logic circuit group 71A, logic circuit group 72A, and storage section 8, and FIG. 4c is ( 2-2), FIG. 4d and FIG. 4e are diagrams showing a thinning mask, and FIG. 5 is a diagram showing a first embodiment of the thinning section 2.
6 is a block diagram showing an example of the storage section 6, FIG. 7 is a diagram showing an example of the relationship between shift registers configuring the storage section 6, and FIG. is a logic circuit diagram showing an example of a circuit corresponding to formula (1), and FIG. 9 is a logic circuit diagram showing an example of a circuit corresponding to formula (1).
10a and 10b are logic circuit diagrams showing an example of a circuit corresponding to (2), and FIGS. The logic circuit diagram shown in FIG. 11 is the formula of the same circuit group 7.
FIG. 3 is a logic circuit diagram showing an example of a circuit corresponding to (3). FIG. 12 is a block diagram showing a second embodiment of the thinning section 2, FIG. 13 is a configuration diagram showing an example of the extraction section 6X, and FIG. 14 is a circuit corresponding to formula (1) in the circuit section 7X. FIG. 15 is a block diagram showing the input/output relationship of the circuit 700X corresponding to circuit equations (2) and (3). FIG. 16a is a block diagram showing an example of the storage section 8X. FIG. 16b shows a logic circuit diagram showing an example of a thinning end detection circuit. In each figure, 1 is an input pattern quantization unit, 2
is the thinning section, 3 is the final thinning diagram, 5 is the control section, 6
A is a temporary input pattern storage section, 71A is an internal pattern plane, 72A is a skeleton pattern plane, 8A is a temporary output pattern storage section, 82 is an AND gate, 8
10 is an OR gate, 810t is its output signal, 6
1a, 61b, 61c, 61d, 61e, 61
f, 61g, 61h are 8 adjacent to shift register 61
Concatenated adjacent shift registers, 62, 63, 64,
65, 66, 67, 68, 69 are AND gates,
710, 71, 71a, 71b, 71c, 71
d, 71e, 71f, 71g, 71h are AND gates, 72 is an AND gate, 73 is an OR gate, 7
41,742,743,744,745,74
6,747,748 are AND gates, 7
401, 7402, 74 are OR gates, 75, 7
6 is AND gate, 6X is pattern extraction section, 7X
is the circuit section, 8X is the temporary output pattern storage section, 61
X, 61Xa, 61Xb, 61Xc, 61Xd, 61
Xe, 61Xf, 61Xg, 61Xh, 61Xi, 61Xj
is a shift register, 710X is an AND gate, 7
1X, 71Xa, 71Xb, 71Xc, 71Xd, 71
Xe, 71Xf, 71Xg, 71Xh are shift registers, 81X is a shift register, 82X, 83X are shift registers, and 810X is an AND gate. 〓〓〓〓〓

Claims (1)

[Claims] 1. While maintaining the continuity of the input binary pattern, create an internal pattern from the top, bottom, left, right, and area of each point at each point of the original pattern, and create a skeletal pattern from the 3 × 3 area of the original pattern and the internal pattern. 1 bit by bit is removed from the original pattern, internal pattern, and skeleton pattern under deletion conditions that are symmetrical in the vertical, horizontal, and diagonal directions at 45 degrees.
Bit thinning processing is performed to create a new original pattern,
a first line thinning section that repeatedly performs the above processing until all line widths are 2 bits or less; and a second line thinning section that receives the output of the first line thinning section and reduces the line width to 1 bit.
A thinning device comprising a thinning section.