JPS62114065A - Information processor - Google Patents

Abstract

PURPOSE:To execute processing at a high speed by separating a calculating part for calculating a processing object itself, and an address calculating part for calculating an address of a memory, and connecting both of them by an exclusive transfer line. CONSTITUTION:A transfer line 50 for transferring an arithmetic output from an address calculating part PVP30B, to a calculating part PIP30A of a processing object is provided, and also a transfer line 60 in the opposite direction is provided. For instance, one (x), (y) address is generated in order by the PVP30B, and with respect to this address (x), (y), a value of (f) (x, y) is calculated by the PVP30B. Subsequently, one-bit information of the PIP30A from an arithmetic part 302B of the PVP30B. In the PIP30A, by receiving its one-bit information, a picture element value of white or black is generated. Also, by sending the address (x), (y) which has been generated by the PVP30B, to an output image memory 20B, the picture element value which has been generated in the PIP30A is written to its address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing apparatus suitable for use, for example, in video image processing.

[Summary of the invention]

This invention provides an apparatus in which a data processing section that reads data from a memory section and performs processing processing is separated into an address calculation section for the memory section and a processing target calculation section to enable high-speed processing. By providing a direct information transmission path with the target calculation unit and exchanging calculation information between both calculation units, the range of processing can be expanded.

[Conventional technology]

Although various video image processing systems have been proposed, this type of system generally includes an input/output section, a memory section, and a data processing section.

This video image processing system is especially useful for data processing.
The applicant previously proposed a system in which the data processing section was separated into an address calculation section for the memory section and a pixel data calculation section for speed ratio (see Japanese Patent Laid-Open No. 58-215813).
.

In other words, if the two calculation units are not separated, the total processing time for both is required, but if they are separated in this way, the processing time is the longer of the two, resulting in faster speeds. processing becomes possible.

Figure 5 shows an example of the configuration of a device that is a further improvement of this image processing device. (hereinafter referred to as 10C), (20) is a memory section (hereinafter referred to as VI
M), this is a human image memory (ν■MIN)
(20A) and output image memory (VrMOUT)
(20B). (40) is a processor (hereinafter referred to as TC) that controls execution and termination of processing.

In this example, the data processing unit 4-11 is a processor system that calculates pixel values (hereinafter referred to as 1/PIP) (30
A) and timing of data flow management and processing such as address management ・1! A system of processors (hereinafter referred to as P
(referred to as "VI") (divided into 30 + 1 >).

l0C(10) is, for example, a video camera 11 from a video camera.
M No. is changed to Al1) and moxibusted to 7゛(digital ll1ri image data, stored in the human image memory (20^), and the processed image is obtained from the output image file (2(ill)). The data is read out, converted to 1)/, and returned to an analog video signal, which can be recorded on, for example, a VTR or supplied to a monitor receiver so that the processed video image can be monitored.

The PVP (30B) that constitutes the data processing unit reads out the image data stored in the input double-image memo (January 2), performs various processing processes on it in the PIF (308), and outputs the processed data. Performs processing to write to image memory (2B).

Writing to and reading from the memory section (20) is performed in units of image groups, ie, one field or one frame. For this reason, human image memory (2^) and (2
Each of B) has a plurality of memories each having a capacity for one field or one frame of image data.

PIF (308) and PVP (30B> basically have the same architecture, and are independent processors consisting of a control section, arithmetic section, memory section, and human output board, and each has a multiprocessor configuration consisting of multiple unit processors. , speeding up of processing is mainly achieved through parallel processing methods.

The PIF (308) has, for example, 60 PRP processors and several sub-processors, and processes IIItI image data from the VIM (20) or generates image data internally. The clock of this p t p (:llA) is TC
(40).

PVP (3011) has 30 pieces of which processor, and the pixel value from VIM (20) '/(7) F
VIM (
20) Check the flow of image data on the inner side.

That is, p v p (3o11) is 71M (2
It generates the address data and the input/output control number fi for the PIP (30A) and supplies them to the VIM (20).
and other control signals, and transfer these to PIF (3
08).

For example, as an example of a simple process, ζ1 "binarizes the value of each pixel in the human-powered double-image memory with a certain dark value" process.
The operations of IF (30^) and PVP (30B) will be explained.

First, input image memory (20^) NiPVP (301
1) One address from 15. Yes, one pixel data is read out. Next, the value of the pixel data read out by the PIF (30^) is binarized using a dark value.

Next, the address to which the calculated value is to be written and a write signal are given to the output image memory (20B) from the PVP (30B).

The above steps are performed for all pixel data for one frame to create binarized image data.

[Problems to be Solved by the Invention] As described above, processing speed can be increased by dividing the data processing unit into the address calculation unit PVP (30B>) and the processing target data value calculation unit PIF (304).

In the case of simple processing such as the process of binarizing each pixel value of the input image memory (20A') with a certain dark value, the PIF (308) and pvp (30B) are completely separated. processing becomes possible.

However, this is not a simple process, and when it is necessary to determine the address of the next data to be read and processed depending on the image content, or when there is no need to calculate pixel values from address information, However, if the calculation sections were completely separated for both sides as described above, processing would no longer be possible.

[Failure to solve the problem]

In this invention, C has a memory section and a data processing section, and the data processing section is the memory section.

The address calculation section is a device that is separated into an address calculation section that generates an address signal, and a processing object calculation section that processes the processing target data read out from the memory section. A direct calculation information transmission path is provided between the processing target calculation unit and the calculation unit to be processed.

(Function) Since calculation outputs can be exchanged between the address calculation section and the processing target IT calculation section, processing according to the image contents can be handled, and the range of processing is increased.

〔Example〕

FIG. 1 shows an embodiment in which the present invention is applied to the above-mentioned video image processing device. In this example, PVP (30
Provide a transmission path (50) that supplies the calculation output from B) to the PIF (30^), and a transmission path (60) that supplies the calculation output from the PIF (308) to the PVP (30B).
will be established. The rest of the structure is the same as the example shown in FIG.

Figure 2 shows p I P (30A) and PVp in Figure 1.
(30B) and VIM (20), and as mentioned above, PIF (308) and (
30B') have the same architecture and are operated by microprograms, and each has a control unit (301A).
and (301B) and calculation section (302^) and (302B
).

In this example, the calculation output from the calculation unit (302^) of the PIF (304) or a part thereof is transferred to the PVP.
It is supplied to the control section (301B) of (30B>) and also supplied to the calculation section (302B) of PVP (30B) as needed.
The output value obtained by the calculation in step B) or a part thereof is supplied to the control section (301^) of the PIF (30^) and, if necessary, the calculation section (302^) of the PIF (30^).

By exchanging a small amount of information between the PIF (308) and the pvp (30[) as described above, the following processing becomes possible.

[Example 1] Display processing of curve f (x, y) = Q This is PVP (30B) (7) from calculation unit (302B)
This is made possible by sending a 1-bit signal to the control section (301^) of the IF (30^). The process of processing will be explained in detail below.

■ Generate one x, y address in sequence at P VP (3011).

■ P V P (30n) and σ)! 1′ completed x
, set the value of r (x+y) for y to rtl-$8
Ru.

■ PVP (30B) 17) f (x
, y) = 0 or not.

■ plp (30/l), and from that 1-bit information r
If (x, -y) = 0, for example, white, r (x,
If y)≠0, for example, a black pixel value is generated.

I ■ Output internal image memory (20B)
30B) send the address generated in ■, and PIF (3
0^), write the is prime value generated in ■ to that address.

As described above, it is possible to obtain image data in which the curve f (x, y) =Q is displayed on the monitor screen as a white curve against a black background.

[Example 2] Boundary tracking of binary image This is from the calculation unit (302A) of PIF (30A>) to pv
This can be done by sending 1-bit information to the control unit (301B) of p (30B).

That is, the PIF (30^) generates 1-bit boundary information from the binary pixel value, supplies this to the control unit (301B) of the PVP (30B), and sets the address for tracking the boundary to the PIF (30^).
It is created in VP (3013).

For example, when generating an address that traces the boundary between the self and black areas of the 24dih image from the upper left to the lower right as shown in Figure 3, the address of point P is output from pvP (30B) and C When, the address of the next boundary is °r! - to be made into two.

That is, for example, r: A of the pixel next to the right in the A P to water direction. I outputted the response and looked at it, I) I
1) If you refer to the boundary information of that point in (30^), you will know that it is not a boundary, so next, for example, specify the -j'l'' point in the vertical direction from that point.

Thereafter, an address can be generated by tracking the boundary while referring to the boundary information from PIF (308) in the same manner.

This boundary tracking enables processing such as determining the length of the boundary, for example.

[Example 3: In the case of 4J interpolation in J image rotation processing, PVP (3011) +7) Arithmetic unit (
3021+) from F T P (30
A) is supplied to the arithmetic unit (302^).

In other words, in the process of creating an image in which both input images are rotated by θ around the IJX point, the output address (X,
As the pixel of Y), it is sufficient to manually output the pixel at the address of (x, y).

Here, the values of x and y are x=Xcosθ+Y sinθ y=-Xsinθ+Y cosθ It is calculated in PVP (30B) as follows. However, X.

The value of y is generally not an integer, and there is no corresponding single human pixel data. So, this (x.

The pixel value that should be at (x, y) is calculated in the PIF (30A) by interpolation from the lIh1 pixel data that actually exists around the address value of y). In this case, if the pixel value of (x, y) is determined by interpolation from the human pixel data of four surrounding points, for example, from each of the four points (x, y),
Interpolation is performed by weighting each pixel data of the four points according to the distance to y). The magnitude of the weighting coefficient for each point can be determined based on the decimal part of the x and y values.

Therefore, the decimal part of the x, y values is used as several bits of information and is sent to the PIF from the calculation unit (302B) of the PVP (30B).
(30^) to the arithmetic unit (3028) and PIP (30
In A), interpolated data is created.

Figure 4 shows an example of the configuration of the control unit when processing is extended by sending 1-bit information from the calculation unit to the control unit as in [Example 1] and [Example 2] of the following 11 examples. It is.

In the figure, (70) is a microprogram controller, and (71) to (74) are microprogram memories. A microprogram controller (70) generates addresses for microprogram memories (71) to (74) via a register (75).

An instruction bit for selecting one of a plurality of instructions of the microprogram controller (70) is obtained from the microprogram memory (71), and this bit is transmitted via a register (76) to select one of the instructions of the microprogram controller (70).
Controller (70) instruction terminal! supplied to

Further, (77) is a selector, to which a plurality of desired 1-bit information is supplied, and the microprogram memory (
72) One of them is selected based on the information read out. This 1-bit information from the selector (77) is supplied to the program controller (70) as a conversion code, which is either incremented by one or supplied to the direct input end as the next address. This information is used to select either the address or another address.

From the microprogram memory (73), for example, I
D.

Information such as the number of loops is obtained, and this is stored in the register (79
z).

Microinstruction information is obtained from the microprogram memory (74) and provided to the arithmetic unit via the register (78).

This microprogram controller (70) is configured to enable one of the three enable signals PL, VECT, and MAP according to the instruction bit. Therefore, one of the registers (79t) to (793) is enabled by the instruction bit, and the address latched therein becomes a direct input to the terminal. Most instructions enable PI. However, in the instruction, whether or not direct manual power is selected depends on the condition code from the selector (77).

The above-mentioned I-pi-I information from the arithmetic unit is used as one manual information of this selector (77), and
If the processing in Example 2) is carried out in ``4'', 1) is selected as necessary according to the selection information from the microprogram memory (72).

The above is a case in which the apparatus of the present invention is applied to video processing, but it goes without saying that it can also be applied to digital processing of audio M'rJ and other fN signals.

〔Effect of the invention〕

According to the present invention, in the device which aims to speed up the °ζ processing by +1 (1 speed) by separating the point calculation unit that calculates the processing z1 image itself and the address calculation unit that calculates the memory address,
By providing a direct transmission path for calculation information between the two calculation units, the range of processing is expanded, such as being able to perform more complex processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of the device of this invention, FIG. 2 is a block diagram of an example of its essential parts, FIG. 3 is a diagram for explaining an example of processing, and FIG. 4 is a diagram of the essential parts of this invention device. An Example Block Diagram FIG. 5 is a block diagram of an example of a previously proposed device. (10) is the human output section, (20) is the memory section, (30A
) is a processor as a processing target calculation unit, (30B) is a processor as an address calculation unit, (50) and (6
0) is an information transmission path. Figure 3 R 7ka Micro C program R controller - RAM 2910 79,
7゜MPM4 MPM3 MPM2
MPMIIHl-L, rj 72J7tl. 1N opening HG2-114065 (6) rυ 1ull - K11 Block 2 of the picture image myri XZ - 5th
figure

Claims (1)

[Claims] It has a memory section and a data processing section, and the data processing section includes an address calculation section that calculates and generates an address signal given to the memory section, and a process that processes target data read out from the memory section. An information processing device that is separate from a target calculation unit, and has a direct calculation information transmission path between the address calculation unit and the processing target calculation unit.