JPS62114055A - Direct memory access control device - Google Patents

Abstract

PURPOSE:To execute a data transfer at high speed when a data is transferred from a memory to memory by a DMA transfer system, by providing each separate address register for read-out and write, and switching and operating both of them. CONSTITUTION:A selecting port 15 is provided in order to inform to a distributor 16 whether a memory to which an access is executed at present is in a read-out side or a write side, and in accordance with the output of this port 15, the distributor 16 distributes the output of a clock port 12 and the output of an enable port 13 to the first address register 17 and the second address register 18. At the time of read-out, the higher rank of an address is set to the register 17, and at the time of write, the higher rank of the address is set to the register 18. Such setting of the higher rank of the respective address to the registers 17, 18 is executed only at the time of a data transfer of the first time, and at the second time and thereafter, the setting is executed only when the higher rank address is changed.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to direct, memory, access (Dir
ect Memory Access; Hereinafter, single K
It relates to an information processing device using a transfer method (abbreviated as DMA), particularly between memory devices or within a memory device.

Control data transfer between memory areas.

This invention relates to a seed control device.

[Background of the invention]

An information processing device using a thermal crystal and a control device has a general configuration as shown in Fig. 2.

Central processing unit (hereinafter abbreviated as CPU) 20. D.M.A.
.

Control device 21. Each memory device 22 has an address.

Bus 25. They are interconnected by a data bus 24. .

DMAtltII controller 21 operates independently of CPU 20 7x.

This is oJ Noh.

As an example, the memory device 22 according to the DMA system [21]
Consider the case of transferring data from an area of a physical foot to another area. DMA control device 211 (1) The configuration is as shown in Fig. 5. LS that performs central control of DMA transfer.
I is called a direct memory access controller (hereinafter abbreviated as DMAC) 5o.・1) MAC50 is a DMA (r 50 to memory device! 122 hair habit
-Address port 5 for outputting the desired address
1, and a data bus 15 for storing data read from the memory device 22 inside the DMAC 50 at -IO time (to read data from the data bus 24).
It has 2. The number of bits required for the address bus 25 is determined by the size of the address space of the system. For example, if the system space is 64KB (kilobyte), the address bus 25 is 16 bits.

It is. However, in recent years, it has become vast, ranging from 16MB (megabyte) to 4GB (gigabyte).

As the system space becomes mainstream, the address bus 25 also increases from 24 bits to 52 bits. Therefore, in order to output addresses with this many bits all at once from the DMAC 50, the number of LSI bins is required, which leads to an increase in the size of the LSI package. When outputting an address from ゛), the address is output using a time division method. - For example, address bus 25 is 52
In the case of bits, the address port 51 is used for only 16 bits, and the 16 bits are output twice by time division to form a 52-bit address. Therefore, an address bus of 1° to 55 is required.

The operation will be explained using FIG. 4. First, the upper 16 bits of the address are output from the address port 51. In order to set this in the address register 55-, the latch clock 15 from the DMAC 50 is output from the clock port 34 shown in FIG.

It will be done. As a result, the upper 16 bits of the address are read at the timing of the latch clock.

is latched in the register 53.

Next, the lower 16 bits of the address are address points 0 and 5.
- Output from 1to 51. At the same time, an enable signal is output from the enable port 35 to enable the output of the address register 35.・As a result, the upper 16 bits of the latched address are output from the address register 55, and the upper 16 bits of this address and the address port 5 of the DMAC 50 are then output.
The lower 16 bits of the address output from address 1 are combined to form address 25 as a 52-bit address.
sent to. That is, a valid address is sent out on the address bus 23.

When the upper 16 bits of the address are output from the address port 51, the 0 output is divided into two at the branch point A, as shown in FIG.
At this time, the DMAC 50 flows to the address balance 25 without going through the memory device 22 shown in FIG.
Perform access to.

Therefore, even if the upper 16 bits of the address flow into the address bus 25 in this way, no change will occur.
Ri^04.

The above is the operation of the DMA control device shown in FIG. 5 at the time of addressing and sending.

Now, let's move on to Part 5, which shows the processing flow of the DMAC50.
The overall processing operation during data transfer will be explained using figures. 5. As shown in FIG. 5, first, in step 40,

The upper address of the read side address of the memory device 22 (source side upper address) is stored in the address register 55.

Next, in step 41, the source side lower a.

The address is output from the address port 51. Then 0,
Step 42 "C-&'! The source measurement upper address set in step 40 and the source address outputted in step 41.
The source data is read from the memory device 22 using the source address and transferred to the DMAC via the data port 52.
Temporarily save to 50. Next, step 5 step 45
Then, the upper address of the storage side address of the memory device 22 (the upper address of the destination side) is set in the address register 55. In step 44, the lower address on the destination side is outputted from the address port 51. In step 45, the destination ■ set in step 45 is set.

The high-order address on the input side and the dian output in step 44.

The data saved in the DMAC5o is transferred to the data using the lower address 11111 on the 7th.
It is output from the boat 52 and written into the memory device 22. 5
In step 46, it is determined whether or not the series of transfers has been completed. If not, the process advances to step 4o. - In this way, conventionally, data is transferred once every 5 rows ((, address () to the address register 55 twice).

The upper address on the source side and the upper address on the destination 0 side) must be set.

Therefore, when data transfer is performed several times, it takes a considerable amount of time, resulting in the problem that high-speed data transfer cannot be performed.・Incidentally, there are 1 references regarding this mallet device d! For example, "+-1o6aa5
o, HD68450YDMAC Manual” (%
Examples include P49 Figure 44 and P50i Figure 45).

[Purpose of the invention]

The purpose of the present invention is to solve the above-mentioned problems of the prior art, and
An object of the present invention is to provide a DMA control device that can perform high-speed data transfer when transferring data from memory to memory using the MA transfer method.

[Summary of the invention]

The LSI that controls DMA transfer, that is, DMA (,') generally outputs addresses in a time-division manner to reduce the number of pins. Therefore, an address register is required externally. However, Notes from memory.

When data is transferred to another address register, the 0 contents of the address register are generally different between the read side and the storage side, so it was necessary to reconfigure the settings each time the address register is accessed. Therefore, in the present invention, separate address registers are provided for reading and writing, and by switching and using both, it is unnecessary to set each time.J5 [Embodiment of the invention] Hereinafter, the present invention An example of this will be explained with reference to FIG.

[1) MAClo used in this embodiment is address port 11. as shown in FIG. clock board 0°
7.

12. Enable boat 15. Has data boat 14.
・DMA shown in the conventional figure 5 in that it is
Same as C+O. However, in addition to that, DMAel 0 &! It has a selection boat 15. This selection port 15 is used to inform the distributor 16 whether the memory 5 to be accessed is the read side or the write side. This selected boat 1
According to the output of 5, the distributor 16 outputs a black signal.

The output of the drive boat 12 and the output of the enable boat 15.

The power is distributed between the first address register 17 and the second address 0 register 18. When reading, the upper part of the address (read address) is set in the first address register 17, and when writing, the upper address (write side address) is set in the first address register 17.

The upper part is set in the second address register 18 d5, and the first address register 17 . 2nd ato.

The upper part of each address is set in the address register 18 only during the first data transfer.・From the second time onwards, unless the upper address changes, ・The DMAC 10 does not output the upper address, and access is performed only by outputting the lower 0° 8′ address. .

For example, a system with a 52-bit address bus 25.

The address port 11 on the stem is 16 pins, and a.

When outputting the address in two time divisions, 1st A.

Address register 17 or second address register 518
The content of ``A'' must be updated in the lower level.

When a carry occurs from an address to a higher address.

only if On average, the ratio is 11 ol per K 65556 (2016 power) times for each address register.

Updates will only be made. Therefore, in normal transfer, 0 has little effect on updating the address register.゛The flowchart in Figure 6 is an address register.

This shows the case where no update occurs. When updating the address register, update the address register for that transfer.

If you consider that the process starts from step 50 in FIG. Therefore, in this embodiment, step 50 is provided only when no update of the address register occurs.
Since this is the first transfer to the right, the upper address (source) of the read side address of the memory device d22.

side upper address) is set in the first address register 17. Next, in step 51, the lower and lower addresses on the source side are output from the address port 11. -And step 52 i'&'! , the source status is read out from the memory device 22 using the source-side upper address set in step 50 and the source-side lower address outputted in step 51, and the source status is read out from the memory device 22 via the data port 14.
Temporarily save it to C10 (.・These steps 5
From step 0 to step 52, an instruction signal is output from the selection board 15 so that the first address register 17 can be controlled. 10 From this K, the distributor 16 is connected to the clock port 12. The enable port 15 is connected to the first address register 17.

Next, step 55, since this is the first transfer.

The upper address (715) of the writing side address of the memory device a22
The host address (higher address on the 1st side) is the 2nd address.

Set in address register 18. Then, the step 546 outputs the lower address on the destination side from the address port 11. Furthermore, in step 55, the di 74 degree tension set in step 55 is
temporarily using the high-order address on the destination scene side and the low-order address on the destination scene side output in step 54.
The data saved in MACl 0 is output from the data boat 14 and written to the memory device 22. Between these steps 55 and 55, an instruction signal is outputted to the selection board 15 so that the second address register 18 can be controlled. As a result, the distributor 16
is Crocbo・-) 12. Enable 15 is connected to second address register 18.
When the number is 10 or more, the first transfer process is completed.

In step 56, it is determined whether the transfer has been completed.

- If the transfer has not been completed, proceed to step 57.・Step 57 The lower address on the source side is output from the address port 11. Step 58 ″c'vs The source side upper address and step set in step 50.

Processing similar to step 52 is performed using the source side lower address outputted in step 57. During this time, the output of the selection board 15 is the same as in steps 50 to 52. Step 59? ” & 0.11 ・Address the lower address on the destination scene side.

Output from sport 11. In step 60, processing similar to step 555 is performed using the upper address on the destination side set in step 55 and the lower address on the destination side outputted in step 59. During this time, the output of the selection board 15 is the same as from step 55 to step 55. This series of processing ends.

The process then proceeds to step 56, where it is determined whether the process is complete or not. - When repeating the loop as described above, the number of steps is 10. It can be seen that the number of steps is 5 in this embodiment, compared to 7 in the conventional case. This difference becomes larger as the number of loops increases, and it can be seen that high-speed transfer can be performed by this embodiment.
15 In general, DMAC often outputs continuous addresses as addresses, but according to this embodiment, it is only necessary to set the upper address in the address register in advance and output it by changing only the lower address. <...Moreover, as mentioned above, the number of processing steps is small.

It can be seen that the embodiment is very effective.　　.

〔Effect of the invention〕

According to the present invention, the memory is transferred using the seed transfer method.

When transferring data from to memory, the number of steps in the processing loop 5 can be reduced, resulting in high speed.

Data transfer can be performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a general information processing device, FIG. 5 is a block diagram showing a conventional machine control device, and FIG. 4 is an address in FIG. 5. An explanatory diagram for explaining the operation at the time of sending, Fig. 5.
The flow of processing during data transfer in the figure. FIG. 6 is a flowchart showing the flow of processing when transferring 15 data in FIG. 10...DMAC 11...Address port 12...Clock boat 15...Enable port 14...Data boat 15...Selection boat 16...Distributor 17...First address register 1 Japan...Second address register] 5 15゜No. II!

Claims (1)

[Claims] (1) Send a read address to the source side memory via the address bus to read data from the source side memory, and send a write address to the destination side memory via the address bus to read the data. By writing the data into the destination memory, data is transmitted from the source memory to the destination memory, and the addresses sent via the address bus are divided into upper and lower addresses and generated in a time-sharing manner. In a direct memory access control device, the upper part is latched in a register first, and when the lower part is generated, the upper part is outputted from the register, and both are sent together. A direct memory device characterized in that a first register for a read address sent to the destination memory and a second register for a write address sent to the destination memory are prepared, and the two are used by switching between them. -Memory access control device.