JPS62113287A - Optical character reader - Google Patents

Abstract

PURPOSE:To improve a recognition processing speed by providing a recognizing means which recognizes graphic characters and a control part which sends an instruction for the storage of binary data in >=2 storage means to a distributing means and supplies information for selecting a storage means to the recognizing means. CONSTITUTION:An OCR consists of a photoelectric conversion part 51, a multi- value data buffer 52, a distributing circuit 53, a recognition part 54, and a control part 55. The distributing circuit has a filter circuit at its front stage and distributes binary data which is converted by the filter circuit to binary data buffers 54a-54c at the rear stage by receiving an instruction from the control part 55. A recognizing circuit 54d selects the binary data buffers 54a-54c on the basis of selection information from the control part 55 to recognize characters. Consequently, a front-rear overlapped part need not be rewritten, so characters are segmented efficiently and a recognition processing speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an optical character reading device, and relates to preprocessing for graphic character recognition.

(Prior Art) FIG. 3 is a block diagram showing the configuration of a conventional optical character reading device (hereinafter abbreviated as OCR).

The OCR includes a photoelectric conversion section 11, a multilevel data buffer 12, a filter circuit 13, a recognition section 14, and a control section 15. Further, the recognition unit 14 includes a binary data buffer 14m and a recognition circuit 14b.

Next, the operation will be explained.

First, graphic characters (hereinafter referred to as characters λ) in the text portion of the form are converted into gradation digital signals by the photoelectric conversion unit 11,
This digital signal is stored in the multilevel data buffer 12. The digital signal output from the multi-level data buffer 12 is binarized and smoothed by the filter circuit 13 and stored in the binary data buffer 14a of the recognition unit 14. The recognition circuit 14b performs recognition processing on this binary data, and outputs the recognition result to the control section 15. Characters are read in this manner. Among these steps, the operation of determining a recognition target range to be recognized for the binary data stored in the binary data panopher 14a is called cutting.

FIG. 4 is an address timing diagram according to the form format. Reference numeral 31 indicates an address timing on the multi-value data buffer 12 determined as the format of the form information, and when this timing is High, the entry frame on the form corresponds.

32 is the range in which one character determined by the above format exists (hereinafter referred to as 1 pitch), and 36
is equivalent to 2 pitches. 301, 302゜303,
304 represents the center address of the ltgh state (of address timing 31).

When cutting out one character Notan, the data output from the multi-value data buffer 12 is for two pitches, and its address timing is shown as 33, 34°35. 33 represents two pitches from 300 to 302 to the left of 301, 34 represents two pitches from 301 to 303, and 35 represents two pitches from 302 to 304.

FIG. 5 is an explanatory diagram showing the correspondence of specific character patterns to the address timings shown in FIG. 4. Reference numeral 41 indicates data output from the multi-level data buffer 12 at an address timing similar to the address timing 31 in FIG. 43
is outputted from the multilevel data buffer 12 at timing 33 of the data 42, converted into binary data by the filter circuit 13, and stored in the binary data buffer 14a.
This is ・yatan as value data. Similarly, 44 is a bang as binary data that is output from the multi-level data buffer 12 at the timing of 34, and 45 is a bang as binary data that is stored in the binary data buffer 14a via the filter circuit 13.

In conventional OCR, after storing the data of the portion shown at timing 33 in FIG. 4 in the two-channel data buffer 14a, the recognition circuit 14b determines the recognition target range of the data in the binary data buffer 14a and performs recognition processing. conduct.

After outputting this recognition result to the control section 15, the multilevel data buffer 12 outputs the portion shown at timing 34 in FIG. 4 in response to an instruction from the control section 15. Next, character reading is performed in a similar manner at timing 35 in FIG. In addition, in the character extraction process that determines the recognition target range, black and black parts that are judged to be unnecessary are deleted from the binary data (hereinafter referred to as white dot conversion), and the remaining characters and black parts are removed. It is to extract.

To explain this with Figure 5, 4 in 43
By turning the part 32 into a white dot, it becomes a tan state as shown by 43-2. The necessary criteria for making white dots is to calculate the area ratio of the rectangular area surrounding 431 and the rectangular area surrounding 432 for the rectangular area surrounding both 431 and 432, and calculate the ratio from a predetermined constant. Possible methods include turning the black/black color (432 in this case) corresponding to a small value into a white dot. As a result of the above character extraction processing, the recognition target range is determined in such a manner that 44 ・nitan is the character 44-2, and 45 noe tan is the 45-2 character tsukutan.

(Problems to be Solved by the Invention) However, in the OCR having the above configuration, the overlapping portions between 301 and 302, between 302 and 303, and between 303 and 304 in FIG. 4 are processed on the binary data buffer 14a. In order to do so, it is necessary to rewrite all the binary data in each section, which poses a problem in that it takes time to cut out characters.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide an optical character reading device that can speed up recognition processing by efficiently cutting out characters.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention is based on binary data obtained by binarizing a gradation digital signal obtained by photoelectrically converting graphic characters on a form. , in an optical character reading device for reading graphical characters, a distributing means for distributing the binary data, a plurality of storage means for storing the binary data distributed by the distributing means, and selection of these storage means. a recognition means for recognizing graphic characters based on the binary data obtained by the above processing; In contrast, a control section is provided for providing information for selecting the storage means.

(Function) According to the present invention, as described above, an optical character reading device (OC
R), the technical means work as follows. The control means acts to give an instruction (timing) to the distribution means to simultaneously store binary data in two or more storage means.

This instruction causes the distribution means to operate to simultaneously store binary data in two or more storage means. Next, the control means are 2
It functions to perform graphic character recognition processing on the binary data stored in the storage means selected by the storage means for which storage of value data has been completed. Therefore, unlike the conventional method, there is no need to rewrite the front and rear au palazzo parts, so characters can be cut out efficiently and the recognition processing speed can be increased.

(Embodiment) FIG. 1 is a block diagram of OCR showing an embodiment of the present invention. This OCR is composed of a photoelectric conversion section 51, a multilevel data buffer 52, a distribution circuit 53, a recognition section 54, and a control section 55. The recognition unit 54 also includes three binary data buffers 54a, 54b, 54c and a recognition circuit 54.
Consists of d. The photoelectric conversion section 51 and the multilevel data buffer 52 are the same as the components with the same names in FIG. The distribution circuit 53 has the same filter circuit as the filter circuit 13 shown in FIG. distribute. Recognition circuit 54d
selects binary data buffers 54a to 54e based on selection information from control section 55 and performs character recognition processing.

A control section 55 controls the entire device.

FIG. 2 is an address timing diagram in this embodiment. In the figure, 61 is the address timing 3 in Figure 4.
This is the same address timing as 2, and is determined by the format of the form information stored in the control unit 55. Also, 601°602, 603, and 604 are 301, 302, and 303 in FIG.

304 and 304 have the same address timing. 62°63
．． 64 is a binary data buffer 54a, 54b.

This is the address timing of the multi-value data buffer 52 corresponding to the binary data stored in 54c.

Next, the operation will be explained.

First, at address timing 62 in FIG. 2, multi-value data is output from the multi-value data buffer 52, and the distribution circuit 53
The data is converted into binary data and stored in the binary data buffer 54a. At this time, at time 601, the distribution circuit 53 switches to transfer binary data to the two-channel data buffers 54a and 54b, and from 601 to 602, binary data is simultaneously transferred to the binary data buffers 54a and 54b. Next, at time 6020, the data transfer from the distribution circuit 53 to the binary data buffer 54a is finished, and the distribution circuit 53
is switched to transfer data to the binary data buffer 54c.

The binary data buffer 54a in which binary data is stored is 6
After 02, it is connected to the recognition circuit 54d. Based on the binary data stored in the 2nd shift data buffer 54a, the fatigue level 54dφ: Tribute; Dankarari Announcement 11
Output to the dark part 55. After this, the binary data buffer 54
The connection between a and the recognition circuit 54d is cut off.

On the other hand, from 602 to 603, binary data is simultaneously transferred from the distribution circuit 53 to the binary data buffers 54b and 54c. At time 6030, the transfer from the distribution circuit 53 to the binary data buffer 54b ends. The binary data buffer 54b includes a binary data buffer 54a and a recognition circuit 54d.
After the connection with the recognition circuit 54d is cut off, the connection is made with the recognition circuit 54d. The recognition circuit 54d performs recognition processing based on the binary data stored in the binary data buffer 54b, and the recognition result is sent to the control unit 5.
Output to 5. Similarly, from 603 to 604,
Binary data is simultaneously transferred from distribution circuit 53 to binary data buffers 54c and 54a. This transfer is 60
The recognition circuit 54d performs recognition processing based on the binary data stored in the binary data buffer 54c after completing the recognition processing using the binary data in the binary data buffer 54b. Such operations are sequentially repeated.

Binary data buffers 54a, 54b, 54c
As shown in FIG. 1, each has status flags A, B, and C indicating whether storage has ended or storage has continued. The recognition circuit 54d monitors the status flags A-C, and under the control of the distribution circuit 53 connects the status flags to the binary data buffer whose storage has ended, and performs recognition processing. Next, after outputting the recognition result to the control unit 55, the recognition circuit 54d sets the status flag of the connected binary data buffer to continue storage and disconnects it. The distribution circuit 53 starts storing binary data when the status flag indicates that storage continues.

Note that if there are two binary data buffers whose status flags A and -C have been stored, selection information is given from the control unit 55 to the recognition circuit 54d, so the recognition circuit 54d uses the selection information to , select the binary data buffer.

As described above, this embodiment has the following effects.

The recognition unit 54 has a plurality of binary data buffers, and a distribution circuit 53 having a filter circuit for converting multivalued data into binary data is provided. Conversion from multivalued data to binary data is performed regarding overlapping portions of characters before and after characters. Since it is no longer necessary to slightly modify the data and store it in a binary data buffer, an improvement in efficiency can be expected. In addition, the recognition circuit 54
d is a binary data buffer 54a to 54c that can be recognized and processed.
is selected and recognition processing is performed, so even if you perform processing such as turning the button data into white dots when cutting out characters, it will not affect the next button after the button, so cut out. The accuracy when determining the recognition target range is not compromised.

By the way, if there is a plurality of binary data buffers that can be recognized, the recognition circuit 54d is configured to select the binary data buffer based on the selection information given to the recognition circuit 54d Ic from the control section, so that the recognition process can be performed accurately. The binary data buffers 54a to 54c can be selected at any time.

In addition, although this example shows the case where there is one recognition circuit,
Even if two or more recognition circuits are connected, the recognition circuit
Since it has a function of selecting a binary data buffer that can be recognized and processed based on selection information given by the control unit,
This does not contradict the explanation of this embodiment in any way. Note that, as a matter of course, in this case, the recognition processing can be performed in parallel, so that the effect of increasing the processing speed can be expected.

(Effects of the Invention) As described above, according to the present invention, there is no need to rewrite the overlapping portions of the preceding and succeeding characters, so that the graphic character recognition process can be performed efficiently and accurately.

[Brief explanation of drawings]

FIG. 1 is a block diagram of OCR showing an embodiment of the present invention.
Fig. 2 is an address timing diagram of the embodiment shown in fd Fig. 1, Fig. 3 is a block diagram showing the configuration of a conventional OCR, Fig. 4 is an address timing diagram of the form 7su-manoto, and Fig. 5 is a character cutting diagram. FIG. 51... Photoelectric conversion unit, 52... Multi-value data buffer, 53... Distribution circuit, 54... Recognition unit, 54a-54
c...binary data buffer, 54d...identification, a circuit, 5
5...Control unit. Book 41 Akira's support for the product of 1 and 41

Claims (1)

[Scope of Claims] An optical character reading device that reads graphic characters based on binary data obtained by binarizing a gradation digital signal obtained by photoelectrically converting graphic characters on a form, comprising: A distribution means for distributing value data, a plurality of storage means for storing the binary data distributed by the distribution means, and recognition of graphic characters based on the binary data obtained by selecting these storage means. and a control unit that instructs the distributing means to simultaneously store binary data in two or more of the storage means and provides information for selecting the storage means to the recognition means. An optical character recognition device characterized by: