JPS62113260A - Timer monitor control system for multi-cpu system - Google Patents

Abstract

PURPOSE:To hold the order of time monitoring operation by allowing a timer interruption handler for a CPU to refer to the status display of its CPU when the holding state of a timer interruption request is reset, and inhibiting interruption processing from being performed originally when the status display indicates that the processing is already finished. CONSTITUTION:Timer interruption handles 112 and 112 receiving time interruption requests generated by the detection parts 111 and 121 in their CPUs perform interruption processes firstly if time request control tables 13-15 precedent to timer request control tables assigned in their CPUs are left in a suspended state, thereby setting the status displays of the assigned CPUs to a processed state after the processes are completed. The timer interruption requests of their CPUs are processed after the completion of process of all precedent timer request control tables 13-15. A timer interruption handler which accepts a timer interruption request after the suspended state is reset performs an interruption process only when the status display of its CPU indicates an unprocessed state. Consequently, timer control in which the order of plural monitor times is held securely becomes possible and the efficiency of processes is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] When multiple CPUs are performing multiple timer monitoring in parallel, some CPUs may not be able to notify timer completion even after the monitoring time has elapsed.

In this case, another CPU supervises the timer monitoring of the preceding CPU to ensure the order of completion notification processing.

[Industrial application field]

The present invention relates to a timer monitoring control method in a multi-CPU system in which parallel processing is performed by a plurality of CPUs.

[Conventional technology]

A series of multiple times arranged in two time series in a multi-CPU system that consists of multiple CPUs, and jobs to be processed at that time are assigned to each CPU, or free CPUs are acquired individually to perform parallel processing. The arrival of is monitored by separate CPUs.

Processes corresponding to each time may be executed while maintaining order.

An example is shown in FIG. In the figure, l to 4 are CPU-1 to CPU, respectively, which constitute a multi-CPU.
-4. Further, numerals 5 to 10 are timer request control tables (TQE: timer queue elements) for managing timer requests, respectively, and TQE-1 to TQE-
It is represented by 6. Each of these TQE-1 to TQE-4 is a control table of O8 that manages the timer interrupt time and the type of service to be processed after two interrupts.

Here, processing of TQE-1 to TQE-4 is currently assigned to CPU-1 to CPU-4, respectively, and each CPU receives the future time in TOD format that manages the corresponding TQE from its own CPU. Set in the clock comparator (time detection section).

It also stores the TQE address in its own CPU's memory.

In this way, after the TQE is allocated to each CPU, each CPU generates a timer interrupt for the corresponding TQE, and the TQE is not released until the reception of the timer interrupt is completed.

Therefore, for example, if CPU-1 is in the suspended state (interrupt acceptance is in the waiting state) from the TQE-1 interrupt occurrence time to the TQE-2 interrupt occurrence time, CPU-2 TQE-2 interrupt processing is executed without waiting for release. The interrupt suspend state occurs during system LRU (processing to flush out old data from the buffer) or when interrupts are disabled.

[Problem that the invention seeks to solve]

As mentioned above, in conventional multi-CPU systems, when performing processing to monitor each of a series of times in a coordinated manner,
When the timer interrupt at the preceding time causes the CPU to enter a suspended state.

If the time becomes longer, a subsequent timer interrupt may occur in the primary CPU, and the interrupt processing may be executed first. In such a case, there is a problem that the order of one-time monitoring cannot be maintained.

[Means for solving problems]

In order to guarantee the order of timer interrupts in a multi-CPU system, the present invention performs interrupt processing in the order of TQEs connected in ascending order of future time.

That is, the CPU that accepted the timer interrupt.

When there is a TQE waiting for an interrupt that precedes the TQE assigned to its own CPU, interrupt processing is started from that TQE and executed up to the interrupt processing of its own TQE.

However, after this, CPtJ of the TQE waiting for the preceding interrupt
If C accepts an interrupt, double processing will occur, so the C
To prevent PtJ from executing interrupt processing, set No processing (No
0operation).

FIG. 1 is a principle diagram of a timer control system according to the present invention.

In the figure, 11 is CPU-1, and 12 is CPU-2. Also, 13.14 are CPU-1 and CPU-
2 is a timer request control table assigned, and 15 is an unallocated timer request control table. These tables are queued in chronological order. 16 and 17 are status displays indicating whether or not the interrupt processing based on the timer request control tables assigned to CPU-1 and CPU-2 has been completed.

Also, in CPU-I CPU-2, 111°12
1 is each assigned timer request control table 13
．． 14 is a time detection unit that monitors the arrival of the time (future time) and generates a timer interrupt request at that time, and 112 and 122 are reception and processing timer interrupt requests generated in the time detection unit, respectively. This is a timer interrupt handler.

When each of the timer interrupt handlers 112 and 122 receives a timer interrupt request generated in the time detection unit in its own CPU, it first precedes the timer request control table assigned to its own CPU in time order. Check whether the timer request control table remains in suspended state B (interrupt request pending state), and if so, execute that interrupt process first, and after the process is finished, execute it on the CPU that was originally assigned to the process. Set the status display to processed. In this way, after all the preceding timer request control table processes have been completed, the timer interrupt request of the own CPU is processed. Further, the timer interrupt handler that receives a timer interrupt request after the suspend state is released executes the interrupt processing only when the status display of its own CPU is unprocessed.

[Operation] The operation of the power type according to the present invention will be explained with reference to FIG. ■ to ■ in the figure indicate control procedures of operation examples.

■ CPU-1 searches the timer request queue.

The first unallocated timer request control table 13 is acquired, and its timer interrupt time (set to 1+) is set in the 9 time detection unit ill.

■CPU-2 receives the next unassigned data in the same way.

The timer request control table 14 is obtained, and the timer interrupt time <11) is set in the time detection unit 121.

■ The time detection unit 111 of the CPU-1 detects 1 time t.

Also raises a timer interrupt request when it arrives. At this time, C
For example, PU-1 is in an interrupt-disabled state, so this timer interrupt request is not accepted and the PU-1 enters a suspended state.

■ 1 with CPU-1. While the timer interrupt request is in the suspended state, the next timer interrupt time t2 arrives, and the time detection unit 121 of the CPU-2 raises the timer interrupt request. In this case, the interrupt request is accepted and the timer interrupt handler 122 is activated.

■ The timer interrupt handler 122 of the CPU-2.

The CPU checks whether there is a timer request control table with a timer interrupt time earlier than the timer interrupt control table 14 of the own CPU, detects the table 13, and performs the interrupt processing first based on the service type. 1
When the processing in step 3 is completed, ■'Set the status display 16 of CPU-1 to "processed".

■ The timer interrupt handler 122 processes the interrupt request from the time detection unit 121 of its own CPU in the same way,
The status display 17 is set to processed.

(2) After time t2, the interrupt inhibited state of CPU-1 is released. Therefore, the interrupt request for time t1 sent from the 9 time detection unit 111 is accepted, and the timer interrupt handler 112 is activated.

■ The timer interrupt handler 112 refers to the status display 16 of its own CPU, and when it identifies that the interrupt has been processed, it does not execute the 9th interrupt processing and uses the unallocated timer for the primary timer monitoring processing. Request control table 15
Let them search.

〔Example〕

FIG. 2 shows the configuration of one embodiment of the present invention.

In the figure, 21 is CPU-1, 22 is C, PU-2
, 23 is system memory, 24 is bus, 211.221
is a time detection unit, 212 and 222 are timer interrupt handlers, 213 and 223 are interrupt processing routines, and 231 to 234 are timer request control tables (TQE-1 to TQE
-4).

235 and 236 represent the status areas of cpu-t and CPU-2.

In each CPU, one time detection unit 211, 221 has TQ
The timer interrupt time taken from E (for example, tI+F
) and a clock device provided in the CPU (not shown)
It consists of a comparator (clock comparator) that compares the real time supplied from the clock. The comparator raises a timer interrupt request until it is reset separately after detecting a match.

Timer interrupt requests are controlled by the CPU.

Interrupt requests may be masked, in which case.

Interrupt requests are not accepted and a suspended state occurs.

When a timer interrupt request is accepted, the timer interrupt handlers 212 and 222 are operated by A shown in the figure.

Execute control of B. A is a control that examines the TQE queue from the beginning and, when a suspended TQE is detected, performs interrupt processing on behalf of the TQE. B is.

After the own CPU has suspended interrupt requests,
When the suspend state is released, it is recognized from the status area (235, 236) of the own CPU whether or not the time monitoring processing that the own CPU is in charge of has been completed, and if the processing has been completed, 1 interrupt processing is performed. This is control to skip execution of routines (213, 223). In other cases,
The processing of the corresponding interrupt processing routine, that is, the processing based on the service type specified by the TQE is executed.

TQE queue (TQE-1 to TQE-4) and each CP
The status areas 235 and 236 of U.

Provided on the system memory 23 and used by each CPU.
.

be made freely accessible.

〔Effect of the invention〕

According to the present invention, it is possible to perform timer control that reliably maintains the order of a plurality of monitoring times, regardless of the state of the CPU responsible for monitoring the preceding time, and it is possible to improve processing efficiency.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of timer control in a conventional multi-CPU system. In Figure 1. 117 CPU-1 12: CPU-2 13-15: Timer request control table 111.121: Time detection section

Claims (1)

[Claims] In a multi-CPU system consisting of a plurality of CPUs (11, 12) and having a time monitoring function that allocates a series of monitoring times to each CPU and causes a timer interrupt to be performed when the time arrives, each CPU ( 11, 12) each have a time detection section (11
1, 121) and timer interrupt handler (112, 12
2) and a status display (16, 17), and a timer interrupt handler (11, 12) for each CPU (11, 12).
2, 122) is a time detection unit (111, 12) of its own CPU.
When a timer interrupt request from 1) is accepted, it is first checked whether the timer interrupt request of the preceding monitoring time is in a pending state, and if it is in a pending state, the interrupt processing for that CPU is handled by the own CPU, and then performs interrupt processing for the timer interrupt request of its own CPU, and also sets the status display of the corresponding CPU to processed when each of the above interrupt processing is completed, and when the pending state of the above timer interrupt request is released. , the timer interrupt handler of the CPU first
1. A timer monitoring control method in a multi-CPU system, characterized in that when the status display of the interrupt is referred to and the status display indicates that the interrupt has been processed, the original interrupt processing is not performed.