JPS6211104Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical deflection circuit for a television receiver, and more particularly to a vertical deflection circuit with improved vertical retrace pulse supply circuit and left/right pincushion correction (hereinafter referred to as DPC) circuit.

In general, the vertical deflection circuit of a television receiver includes a deflection coil as well as a device that corrects left and right pincushion distortion.
A DPC circuit (saturable reactor) is loaded so that a current flows through the deflection coil to correct the distortion. This circuit is constructed as shown in Figure 1, and a vertical deflection coil (referred to as a vertical coil) DY is connected to the output terminals of vertical deflection output transistors Q ₁ and Q ₂ that perform push-pull operation via an output coupling capacitor C ₁ . There is. This deflection coil DY is
It is grounded via a resistor R _F.

At the connection point a between this vertical coil DY and the output coupling capacitor _C1 , _a capacitor _C2 is connected via a resistor R1.
A parallel circuit of correction winding W ₁ of DPC transformer T ₁ is connected to the correction winding W 1 of DPC transformer T ₁ .
W ₂ is connected in series with a horizontal coil (not shown).

At the connection point b between the resistor _R1 , the capacitor _C2 , and the correction winding _W1 , there is a resistor for supplying a DC bias current that optimizes the operating point of the DPC transformer _T1 .
R ₂ is connected. Also, at point a, there is a resistance R ₃ and a resistance
R ₄ are connected in series, the anode of a diode D ₁ is connected to the connection point c of these resistors R ₃ and R ₄ , and a blanking transistor Q ₃ is connected to the cathode of this diode D ₁ .
The base of is connected.

Note that a horizontal retrace pulse is also supplied to the base of this transistor _Q3 , but it is omitted in the figure.

As for the voltage at each point, a voltage waveform in which the potential becomes high during the retrace period as shown in FIG. 2a at point a is obtained. As a result of integrating this voltage with resistor _R1 and capacitor C, the high frequency component is attenuated at point b as shown in Figure 2b.
A parabolic voltage as shown in appears and the correction winding W ₁
A parabolic correction current as shown in FIG. 2f is generated.
Also, at point c, the voltage at point a is connected to resistor R ₃ and resistor
The voltage waveform divided to a predetermined level by R ₄ is shown in Figure 2c.
It appears as shown in . (Vs in the figure indicates the cut-off voltage level of transistor _Q3 .) Furthermore, since the video signal (see figure 2 d) is input to the base of blanking transistor _Q3 (point d in figure 1), At the output terminal e of the transistor _Q3 , a blanked video signal is obtained as shown in FIG. 2e.

In the above circuit, the retrace pulse supply circuit and
Since each DPC circuit serves as a load for the vertical deflection circuit, the power consumption is high and the circuit configuration is not reasonable.

The present invention was developed in view of the above-mentioned points, and a diode is forwardly connected to the connection point between the output coupling capacitor of the vertical deflection circuit and the vertical coil via a voltage dividing resistor to obtain a blanking output. In addition, the present invention aims to provide a vertical deflection circuit in which the correction windings and integration circuits of the left and right pincushion correction transformers are also connected to this voltage dividing resistor, thereby streamlining the circuit configuration and reducing power consumption. be.

The present invention will be described below with reference to an embodiment shown in FIG. A vertical coil DY is connected to the output terminals of the vertical deflection output transistors Q ₁ and Q ₂ via an output coupling capacitor C ₁ , and a resistor R is connected to the connection point a between the output coupling capacitor C ₁ and the deflection coil DY. ₇
and capacitor C ₂ through a series circuit of resistor R ₈ and
A parallel circuit of correction winding W ₁ of DPC transformer T ₁ is connected.

A resistor R 2 for DC bias current supply is connected to the connection point b between this capacitor C ₂ and correction winding W ₁ and the above-mentioned resistor R ₈ , and the correction winding _{W 2 of} the correction transformer T ₁ is not shown. It is connected in series with the horizontal deflection coil.

On the other hand, the anode of a diode _D1 is connected to the connection point c between the resistor _R7 and the resistor _R8 , and the cathode of this diode _D1 is connected to the base of a blanking transistor _Q3 , and a separate horizontal blanking line is connected. This transistor _Q3 is controlled together with the pulse.

In the circuit configured above, the important thing is the resistance
By appropriately selecting the sum of _R7 and resistor _R8 ( _R7 + _R8 ) and the ratio ( _R8 / _R7 ), the level of the retrace pulse voltage and the DPC
The goal is to set the voltage level to an optimal value.

Generally, the amplitude of the output voltage at point a is
If the amplitude at point Va and b is Vb, then Va≫Vb.

Therefore, by making R ₇ + R ₈ equivalent to the resistance R ₁ in the conventional example (Fig. 1), and by making R ₈ /R ₇ equal to R ₄ /R ₃ in Fig. 1, the operation can be improved. It can be made the same as the conventional example.

Therefore, in the conventional example, power was consumed in the DPC circuit through resistor R ₁ , and power was consumed in resistors R ₃ and R ₄ , whereas in the present invention, power is consumed in the DPC circuit through resistor R 1, and power is consumed in resistors R 3 and R
The amount of power consumed by R ₃ and R ₄ can be saved.

As described above, the present invention has the advantage that the circuit configuration can be rationalized without affecting the circuit operation at all, and power consumption can also be suppressed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a vertical retrace pulse supply section and a left/right pincushion distortion correction circuit section in a vertical deflection circuit of a conventional television receiver; FIGS. 2a to 2f are output waveform diagrams at each point of the same circuit; FIG. 3 is a circuit diagram of a vertical deflection circuit according to an embodiment of the present invention. Q ₁ , Q ₂ ... Vertical deflection output transistor, C ₁ ...
...Output coupling capacitor, DY...Deflection coil, W ₁
...Correction winding, W ₂ ...Winding to be corrected, C ₂ ... Integrating capacitor, D ₁ ... Diode, Q ₃ ... Blanking transistor, R ₇ , R ₈ ... Resistance.

Claims (1)

[Claims for Utility Model Registration] A vertical deflection coil connected to the output end of a vertical output circuit via an output coupling capacitor, and a series circuit of a plurality of resistors connected to the connection point between the coupling capacitor and the vertical deflection coil. A blanking line having a parallel connection between the primary windings of the connected left and right pincushion distortion correction transformers and a capacitor, and a diode having one end connected to the connection point of the plurality of resistors and the other end connected to the video signal path. a vertical deflection circuit comprising means.