JPS62109340A - Master-slice substrate - Google Patents

Abstract

PURPOSE:To obtain a high density master-slice substrate by disposing specific first - fourth basic cell group composed of MISFET pairs by a specific method to form various logic circuits only by the alteration of metal wiring level. CONSTITUTION:l-Pieces of MISFET pairs are arranged linearly to form the first basic cell group 1, (m) pieces of MISFET pairs are linearly arranged, all first conductivity type MISFETs are connected each other at gate electrodes 11, all electrodes 8 opposite side to a second conductivity type MOSFETs are connected with each other, all gate electrodes 12 of the second conductivity type MISFETs are conneced with each other to form second basic cell group 2, and the cell group composed of n pieces of MISFET pairs composed in the same configuration as the group 2 as the third basic cell group 3. The first - third basic cell groups 1-3 are sequentially arranged in one row as a unit row 28, a plurality of unit rows 28 are aligned to become source symmetry as a unit block, a block with one or more unit blocks sequentially disposed, and a block with the same number of unit rows 28 as fourth basic cells of the same configuration as the group 1 ared aligned therewith.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention combines a 10-gram blue 4-quart array and a gate array on a 1% master slice substrate, and has an active layer of 2
The present invention relates to a CMO8 type master slice substrate that is a layer.

(Prior Art) The structure of a cMOS type programmable logic array ([FPLA]) conventionally used in semiconductor integrated circuits consists of an AND plane 85 and an OR plane 87, as shown in FIG.
It consists of 1. AND plane 85108 and PMO
There are 8 FET groups 106 to 06 groups.

Also, in this case, the PLA input line 84 and the product term line 86.

Further, the product term line 86 and the output line 88 were orthogonal. (R, HoKRAMBE, Journal Competition Opu Solid State Circuit, : R, HoKRAMBE
CK, Journal of 5olid-5t
ate cir-cuits, Vol, 5c-t
7t Nn3. pp614-619 JuneMata, P
When constructing a sequential circuit with LA, there is a method of directly feeding back a portion 100 of the outputs of the output registers 89 and 1 to the input registers &, as shown in FIG. Also, in this case, %f(7)7! is stored in register 83.89. It is necessary to tighten and design the J Tsugu, 70 Tsubu, etc.

(Problems to be Solved by the Invention) In the conventional PLA described above, when the scale of one circuit changes depending on the number of inputs, the number of product terms, the number of outputs, etc., its shape changes in the two-dimensional direction VC. As a result, when a plurality of PLAs are laid out on a chip, there are drawbacks that as soon as gaps are created, it becomes difficult to increase the density, and wiring of input/output signal lines and t-source lines becomes complicated. In addition, in order to configure a sequential circuit, not only a PLA but also a clip flop must be used as shown in FIG. It was necessary to prepare a defensive position in advance. The seven lip-flops that are prepared can only achieve certain functions. Therefore, it was necessary to redesign not only the metal wiring level but also the previous level circuit such as KVi and another 7-lip-flop circuit to realize a new function and a circuit with a capability exceeding that. There was a drawback that the period increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-density master slice substrate that allows various logic circuits to be realized only by changing the metal wiring level.

(Means for solving the problem) If the present invention is used, the MISFET of the first conductivity type and the MISFET of the second conductivity type can be used.
The first MISFBT is provided with one MISFBT of conductivity type, and these are arranged on the left and right and in the direction of the drain current.
Form a SFET pair, one of this pair (l is any integer)
A first basic cell group is arranged vertically in a straight line in a direction perpendicular to the drain current direction, and m second MISFET pairs having the same configuration as the first MISFET pair (m is an arbitrary integer) are provided. The drains are arranged in a straight line in the direction perpendicular to the DC direction, and all the gate electrodes of the first four-voltage type MISFET are connected to each other by vc, and the second
All the electrodes located on the opposite side of the ISFET are connected to each other, and all the gate electrodes of the second fat-shaped MISFE'l' are connected to each other to form a second basic cell group,
A cell group having the same configuration as the second basic cell group and consisting of n (n is an arbitrary integer) MISFBT pairs is defined as a third basic cell group, and The cell group, the second basic cell group, and the third basic cell group are arranged in a line in order in a direction perpendicular to the drain current direction to form a unit column,
A block in which a plurality of unit rows are line-symmetrically arranged in the drain current direction to form a unit block, and one or more of the unit blocks are sequentially arranged in a direction perpendicular to the drain current direction; A master slice substrate is obtained, characterized in that blocks in which M4 basic cell groups having the same structure as the basic cell group are arranged in the drain current direction in the same number as the unit columns are arranged in a direction perpendicular to the drain current direction. It will be done.

(Example) The present invention will be explained using examples.

Figure 1 (eJ is a gate array consisting of MO8I"gT unit rows 27 and CMO8 laid out on a substrate (hereinafter referred to as G, A,
2 is a diagram showing the arrangement of a row 29 of unit cells (hereinafter abbreviated as G cells) 1 (hereinafter abbreviated as G, A basic cell group) for producing a unit cell (hereinafter abbreviated as G cell).

The contents of the basic cell group 29 for the MO8FETO8FET upper row 27 are shown in FIG. 1(a). Figure 1(a) is a schematic diagram showing the layout of the created hK)SPET, Figure 1(b)
) is an equivalent circuit diagram of the circuit consisting of the MOSFET shown in FIG. 1(a).

In the figure, 1 is the basic cell group for G, A, nMO8F
G, A of 0MO8 configuration consisting of ET, pMO8FET force 1
, one cell (l is 2 or more) is prepared.

6 is a polysilicon gate electrode for nMO8FgT, 7 is a polysilicon gate electrode for pMO8FET, 4 kenM
Source or drain electrode of O8FgT, 5 is pMO8
This is the source or drain electrode of the FET.

2 is a basic cell group for producing a PLA with 0MO8 configuration, and the cell is an nM cell having a commonly connected source electrode 8 and a commonly connected polysilicon gate electrode 11.
O3Fl: T row and commonly connected gate electrode 1
Each of m n-channel % p-channel MOS FETs is prepared. However, f'vlO8F of basic cell group l for G, A,
The channel width is narrower than that of ET. 3 has the same channel width as the basic cell group 2, and n MOSFETs are prepared for each of the nMO8FgT array and pMO8)'ET array e, p, and h, which are arranged and connected in the same way.

In the MO8FET unit row shown in FIG. 1(e), there is a G.

A, one basic cell group 1, and one basic cell group 2.3 are arranged in a direction perpendicular to the drain flow.

A layout diagram of a unit block 13 created by arranging a plurality of unit columns r/c in the drain current direction and its equivalent circuit diagram are shown in FIG.
8FET unit rows 28 unit rows 1105F'r unit rows 27 and MO8FET unit rows 28, which have been moved so as to be line symmetrical with respect to the direction perpendicular to the in-current direction, are arranged in the drain current direction. Also, the nearest MO of the same conductivity type
The source or drain electrodes of the 8FETs are connected.

G, A, and base non-cell groups 29 are also arranged and connected in the same manner.

MO8FET unit string 27 unit string (), A described above.

The following shows a row in which an arbitrary circuit is created using a master slice substrate in which the basic cell group 29 is laid out as shown in FIG.

In the master slice board mentioned above, hJO8PE
m G, A, cells are lined up in the direction perpendicular to the drain current of T, and by using two of these G, A, cells to form metal wiring a63,64, a D type 7 lip-flop (D -F/F) can be produced.

Figure 2 fat is G, A, and D-F made using two cells.
Is there an equivalent circuit diagram for /F? Figure 2 fb) is the tabulated D-
It is a schematic diagram of the layout of F/F.

Note that the terminal names in the figure match those in Figure 2 (al, fb). By using this D-F/F, an input/output register can be manufactured.

In FIG. 3, the basic cell 2 described above is used, and input signals A,
Output signal f for B, C, and D, = B + D.

An example of creating a combinational circuit that outputs f*=A+C will be shown. Figure 3 fat is an equivalent circuit diagram, Figure 3 (b), (C
) shows the layout fu corresponding to FIG. 3 (al). In this example, a circuit is fabricated using only four columns of basic cell group 2.

In the figure, 35. 36. 45. 47. 48 is the second layer metal wiring; 37. 38. 46 is second layer metal wiring, 22 n pMO8F'iDT, 25 u
n MOSFET Te1) Le. In addition, as described later,
PLA (7) AND plane NOR using basic unit cell group 2
When an array is created, 38.48 is the current power line, 35.45 is the input edge, and 36.37.46.47 is the product term line. 39 is the first layer metal 4 wiring and MOSFET
6 a contact hole for connection, 4o a through hole for connecting the first layer metal 4 wiring and the second layer metal wiring 8;
It means a hole created by simultaneously forming a 1t contact hole and a through hole. Similar metal arrangement & I can be performed in the basic cell group 3 to create an arbitrary NO circuit.

FIG. 4(a) shows QA, baseless cell group 1. j, i using main cell group 2.3, a, G, A, inverter, basic cell group 2
, 3 to create a NOR array, and inverter #72 to N0
R7 Ray 73"?'AN1) Hei 1] fi70-), N0
Create an oit plane 71 with R7 and inverter group 75 and create a PLA-9, create a combinational circuit that outputs an output signal, I' = A-g + A-C for input (N No. l (, C) If t, r, = int te, 36°, AND
``F[fi70 NOR7 Ray 73 basic cell group 2,
The N0R7 ray 74 in the 0RXJiLi 71 is manufactured using the basic cell group 3. In this example, MO8 lined up with +AVC
3 FET unit rows and the next stage [LSL” G in the ET unit row
, A. pLh is produced using cells.

In the figure, 80 is pMO8PET, 81 is 108 to n
FET.

76 is an input line to PLA, 77.78 is a product term line, 79 is an output line from l'LA, and 48 is an ilLl current line.

In addition, in FIG. 4(a), MO8F'ETμ, which is not necessary for circuit creation, is drawn as a continuous circuit for convenience.

It can be seen that any combinatorial circuit can be created using the above side force 1.

FIG. 4(b) In this example, input/output registers created using basic cell group 1 for G, A, and basic cell group 1 for G, A, are further layered on the PLA created using basic cell group 1 for G, A, and basic cell group 2.38. It is a schematic diagram showing a case.

In the figure, reference numeral 83 indicates a manual register, an AND plane forming 85 HPLA, and an OR thousand-field 89 output register forming 871'1 PLA. Also, 82 is an input line to the circuit, 84 is an input line to PLA, 86 is a product term line, and 88 is PL
The output line from A, 90 is the output line from the circuit.

As shown in the figure, in the PLA with input/output registers manufactured using the present invention, signals flow linearly downward from the upper blade S in the figure.

FIG. 5 is a layout diagram when a certain number of PLAs are created.

In the figure, 85 is an AND plane, 87 is an OR plane 8
4 is an input line, 86 is a product term line, and wings are output lines.

If the present invention is used, (number of inputs, number of product terms, number of outputs) becomes (1
m r Sm + 51), (1m, Sm, Omaro),
("* r Sa r Os ) and to efficiently arrange different circuits and eliminate the extra gap that exists between PLAs.
It will be possible to increase the degree of integration.)
Ru.

However, s +, 8th, S, ≦m, Ox, Ox,
On≦n.

FIG. 6 shows a PLA sequential circuit realized using this master slice substrate and metal wiring. 91
．． 92 corresponds to the circuit shown in FIG. 2(a), 91 is an input D latch, and 92 is an output D latch. 93
94 is a first clock signal line to the input D latch, and 94 is a second clock signal line to the output D latch. 95 is a MOSFE consisting of 2.3 basic cell groups in FIG. 1(a).
Corresponds to group T.

The output 96 of the input D latch 91 is the positive and negative one word of the input 97 to the input D latch, and is directly connected to the AND plane NO of the PLA.
The outputs 98 of the output D latch 92 are the positive and negative inputs to the R array, and the positive and negative outputs of the outputs 99 from the NOR array in the OR plane of the PLA, respectively.

It is a reverse output. 100 is the seventh output D latch.
The figure shows a case in which the input D latch and the output D latch of the PLA are used together.
09 is input to the second)' LA 103, and the output 1 (17, 108 from the NOR array in the OR plane of the third)' LA is input to the second PLA 103 through the D latch 109. 106 is the first PLA
101 OR in-plane NOR array 7) > with the output of D
It is input to the fourth PLA 104 through a latch 1098.

In this example, nMO8F in basic cell group 2.3
Although the gate electrodes of gT and pMO8f''ET are made separately, there is no problem even if a commonly connected polysilicon gate electrode is used.

〔Effect of the invention〕

As explained above, when developing an integrated circuit, if a groove bottom master slice substrate according to the present invention is prepared in advance, the following effects can be obtained.

First, 2u C1vlO8 type and other types of circuits can be created using the minimum necessary Mo5t"ET unit column and G, A, basic cell groups. As a result, the remaining MO8F'E
The T unit column and the G, A, basic cell groups can be used to create other circuits.

Second, when creating a plurality of circuits, the gaps between the circuits can be made smaller than in the past, making it possible to create highly integrated circuits.

Third, since the necessary 7-rig frogs can be created in the required locations by simply changing the metal wiring, any sequential circuit can be developed in a short time.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the layout of MO8F'FJT in the master slice board used in the present invention, and Fig. 2 is an equivalent circuit when an I)-F/F is created using the present invention. and a layout diagram, FIG. 3 is a circuit and layout diagram of an arbitrary NOR circuit created using the present invention, and a layout diagram, and FIG. 4 is a configuration when an arbitrary combinational circuit is created using the present invention. FIG. 5 shows that a large number of PLAs were created using the present invention and 7. : Layout diagram of each PLA in case, No. 6
The figure shows a PLA with input/output registers when creating a circuit where part of the output signal is fed back to the input signal.
FIG. 7 shows the configuration diagram of PliA when using the present invention.
FIG. 8 is a configuration diagram of a PLA with a CMOS configuration in the conventional method, and FIG. 9 is a configuration diagram of a PLA with input/output registers in the conventional method. In the figure, 1 to 3 are basic cell groups, 4.5.8.9.10 are source or drain electrodes, 6.7.11.12 are gate electrodes, 21 to 23, 80 are pMO8FETs, 24 to 2
6.81 is nMO81”BT, 27.28 is unit column, 1
3 is a unit block, 14 is a block of basic cell group for gate array, 63.35°36, 45.47.48 is first layer metal wiring, 64.37.38°46 is second layer metal arrangement, 30.35.45. is the input line to NOR Louis, 31.32.36.37.46.47 is the product term line,
33, 38.48 are power lines, 34 is a GND line, 39 is a contact hole, 40 is a through hole, 41 is a contact hole and a through hole, 70.85 is an AND plane 71
, 87 is the OR plane, 72.75 is the inverter group. line, 79.88.99 is the output line of the PLA power), 82 is the input line, 90 is the output line, 93 is the clock signal, and 100 is the feedback line. Representative Patent Attorney Susumu Uchihara 1, - ゛(za j: KE L door 4FA15T'e)vtp
4. y/l); '/-su! l”?I2)”
Rain 17-ni 2: Basic 2-field for NOR play
8; source fJ-3, ~ OR array for atrophy n
y: Torrein Denseki Vza: JLa Stand”l, 7. //, /2; K-) tbh21
, 22.23; FMO5EFT24, 25.26
,' nM05FETZ? , 28; Single 4111 I3 stand 1 block Fig. 1 (C block 3: $ stand) Lock I4;
7.2F! : Tomari ≧ 4 ηszY; Basic cell group for lowering the cage Fig. 2 (α) Fig. 2 (b) 2, pM05FET 24, nMO5FFT 63, 11th eye, Otori Kosen Otsu 4. Zth layer Gimhae wiring Figure 4 CQ) 7 (7; AND + original '7/: OR + surface 72.76: Inverter group 737
4; NOR array 7; input to PLA
77.7θ; Heavy Responsibility 1 Blue Collection? 9; f'LA
Kaa et al.'s lightning power feeling 807 FMO5FE
T6f: NMO5FET dθ
;Electric wire t: back. Fig. 4(b) 63; λ Calecista 87: AND+plane F15
;QR+plane θ9; Wealthy star 52
; Input photoelectric θ4: Input edge 86 to PLA
; n around 71-collection 8θ; output edge of FLA force ＼ et al. 90; wealth r qi 5th figure σσ, gopu 6th figure qI; D latch for input 9? ；Rasenq3 for comparison
．． ? 4; Clock words '15; MO5F
ETrfri6,97. Data θ, qq; No. I collection f00; Feed block R Fig. 7 a Fig. F1a 135: AND+L F3'/; OR
Plane 105.106; PMO5FIJt'4
107,10il; NMO3FE
T-kun sheep θ4: PLAI7) Heka N spring
θ6; Katako Kikki θθ; = Toukenshu No. 9

Claims (1)

[Claims] MISFET of first conductivity type and MISFET of second conductivity type
One ET is provided, and these are placed on the left and right and in the drain current direction to form a first MISFET pair, and l (l is any integer) of these pairs are arranged in a straight line in the direction perpendicular to the drain current direction. to form the first basic cell group,
a second MISF having the same configuration as the first MISFET pair;
m ET pairs (m is any integer) are arranged in a straight line in a direction perpendicular to the drain current direction, and a MISFET of the first conductivity type is formed.
All the gate electrodes of the MISFET of the second conductivity type are connected to each other, and all the electrodes located on the opposite side of the MISFET of the second conductivity type when viewed from the gate electrode are connected to each other.
All the gate electrodes of the ETs are connected to each other to form a second basic cell group, which has the same configuration as the second basic cell group and is composed of n (n is any integer) third MISFET pairs. The configured cell group is a third basic cell group, and the first basic cell group, second basic cell group, and third basic cell group are arranged in a line in order in the direction perpendicular to the drain current direction to form a unit. A block in which a plurality of unit columns are line-symmetrically arranged in the drain current direction to form a unit block, and one or more of the unit blocks are sequentially arranged in a direction perpendicular to the drain current direction; A master slice characterized in that a block in which a fourth basic cell group having the same structure as the first basic cell group is arranged in the drain current direction in the same number as the unit rows is arranged in a direction perpendicular to the drain current direction. substrate.