JPS62109330A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the density of elements and to microminiaturize a semiconductor device by deleting the corners of pads opposed to binding wirings to prevent the pads adjacent to the wirings from electrically shortcircuiting, thereby reducing the interval of the pads. CONSTITUTION:Deleted faces 6a, 6b, 6c are respectively formed at the corners of adjacent pads, opposed to wirings led from the adjacent pads of the corners of pads 4a-4c. According to this construction, wirings 5a-5c lef from the pads 4a-4c do not exist on the corners of the adjacent pads. Therefore, the intervals of the pads can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device having a chip forming an integrated circuit.

[Conventional technology]

Electrical connections between the bonding pads of the chip forming the integrated circuit and the bonding areas of, for example, inner leads provided outside the chip are made via bonding wires made of gold or aluminum. These electrodes and wires are bonded by, for example, an ultrasonic bonding method or a thermocompression bonding method. Here, the planar shape of the bonding pad of the chip has conventionally been determined by, for example, "Nikkei Electronics", separate volume [Micro Devices J No. 2, P140-141 (June 1984).
It is rectangular as shown in the Nikkei McGraw-Hill Rei issue published on May 11th.

Incidentally, the distance between a plurality of pads arranged on a chip is becoming smaller as the density of semiconductor elements becomes higher. This is because, while the number of terminals of a package, that is, the number of pads on a chip increases as the density and integration of devices become higher, the size of the chip itself does not increase.

[Problem that the invention seeks to solve]

For this reason, with conventional pads having a rectangular planar shape, even when wire bonding is controlled with high precision, there is a high probability that the wire and the pad will be electrically shorted. This situation will be explained with reference to FIGS. 3 and 4.

Figure 3 shows the chip mounted in a ceramic package.
FIG. 3 is a plan view showing a state in which wire bonding has been performed.

A chip 2 is mounted on the center portion of the ceramic substrate 1, and inner leads 3 extend from the side portions of the substrate 1. The plurality of inner leads 3 correspond to the plurality of bonding pads 4 on the chip 2, and the bonding area at the tip of the inner lead 3 and the pad 4 correspond to each other.
A bonding wire 5 is provided between the two. As you can clearly see from the figure, the wires led out from the pads at the center of each of the four sides of the chip are almost perpendicular to the sides of the chip, but the wires led out from the pads near the four corners of the chip are It will intersect diagonally with the sides of .

FIG. 4(a) shows pads 4a near the four corners of the chip.

This shows a case where the interval between 4b and 4G is relatively large.

In this case, for example, the distance between the wire 5a led out from the pad 4a and the corner of the adjacent pad 4b is kept relatively large, so that the probability that they will be electrically shorted is small. FIG. 4(b) shows a case where the spacing between the pads 48 to 4C near the four sides of the chip is relatively small. In this case, for example, since the wire 5a led out from the pad 4a passes above the corner of the adjacent pad 4b, there is a high probability that these will be electrically short-circuited. Particularly, when the wires 3a to 3C are wedge-bonded to the pads 2a to 2C using the ultrasonic method as shown in the figure, short circuits are likely to occur because the wires pass through a low position.

Therefore, the present invention aims to solve the problem when the spacing between pads on a chip becomes smaller due to the increase in density and miniaturization of semiconductor devices.
This is an attempt to solve the problem of the prior art in that a wire led out from a pad tends to be electrically short-circuited with an adjacent pad.

[Means for solving problems]

In order to solve the above-mentioned problems, the semiconductor device according to the present invention provides a bonding wire led out from a pad (-) among a plurality of bonding pads to a bonding area outside the chip, while an adjacent pad (-) It is characterized by cutting grooves at the corners of the wire.

(Function) Since the above means is adopted, in the semiconductor device according to the present invention, the corners of adjacent pads do not exist below the wire led out from one pad, and therefore the spacing between the pads is reduced. Even when the wire is small and the height over which the wire extends is low, the linear distance between this wire and the pad adjacent to it remains relatively large.

[Embodiments of the invention]

Hereinafter, some embodiments of the present invention will be described with reference to FIGS. 1 and 2 of the accompanying drawings.

FIG. 1 is a plan view of the vicinity of a corner of a chip of a semiconductor device according to a first embodiment, and corresponds to the conventional example shown in FIG. 4(b). This is different from the one shown in FIG. 4(b) in that each of the pads 4a to 4C has a cut-off surface 6a at the corner that faces the wire led out from the adjacent pad.

6b and 6c are formed. Note that the shaved surfaces 6a to 6C form an angle of 45 degrees with respect to the sides of the pads 4a to 4C.

According to the configuration shown in FIG. 1, the wire led out from the pad does not lie on the corner of the adjacent pad. Therefore, even if, for example, the aluminum wire is wedge-bonded to the pad and the wire is led out from a low position (close to the chip), there will be no electrical short-circuit between the pad and the wire. As a result, the spacing between each pad can be reduced. However, since the direction in which the wire is led out from the pad is different on the right side and the left side of the chip side as shown in FIG. 3, it is necessary to make the corners forming the scraped surfaces different accordingly.

FIG. 2 is a plan view of the vicinity of a corner of a chip of a semiconductor device according to a second embodiment. -The difference between this and the one in FIG. 1 is that, among the corners of each pad 4a to 4C, two corners on the side closer to the edge of the chip 2 have a cut-off surface 6a.
~6c, 7a~7C are provided. In addition, also in this example, the angle between the cut surfaces 6a to 6c, 7a to 7C and the sides of the pads 4a to 4C is 45 degrees.

According to the configuration of FIG. 2, the wires leading out of the pads do not lie over the corners of adjacent pads. As a result, the spacing between each pad can be reduced. For example, when the corner of a 110 μm x 110 μm pad is grooved by 15 μm, the pad spacing will be reduced from 200 μm to 135 μm.
m. Further, since the cut surfaces are formed at the two corners of the pad, the pads may have the same shape whether near one corner or the other corner on each side of the chip.

That is, when the wire is led out to the lower right of the pad as shown in FIG. 2, for example, the wire 5b and the cut surface 6C face each other, but when the wire is led out to the lower left, for example, the wire 5b and the cut surface 6C face each other. 7a will face each other, and there is no need to change the position where the cut surface is formed.

The present invention is not limited to the embodiments described above, and various modifications are possible. For example, the shaved surface may have an angle other than 45 degrees, and the angle may vary depending on the position of the pad on the chip. Further, the cut surface may be formed into a circular arc shape.

On the other hand, the bonding wire is not limited to those made of aluminum, and the bonding method is not limited to the wedge bonding method using ultrasonic waves.

(Effects of the Invention) As described above, in the present invention, for a bonding wire led from a pad on a chip to a bonding area outside a chip, grooves are formed in the corners of other adjacent pads opposite to the bonding wire. I decided to do this, so
The probability of electrical short-circuiting between pads adjacent to bonding wires is significantly reduced, and therefore, it is possible to obtain a semiconductor device with high density and miniaturized elements by reducing the spacing between the pads.

[Brief explanation of drawings]

FIG. 1 is a plan view of the vicinity of a corner of a chip of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view of the vicinity of a corner of a chip of another embodiment, and FIG. FIG. 4 is a plan view of the vicinity of a corner of a chip of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Ceramic board, 2... Chip, 3... Inner lead, 4, 4a-4C... Bonding pad, 5.5a-5C... Bonding wire, 68-
6c, 7a to 7G...Removed surfaces.

Claims (1)

[Claims] 1. In a semiconductor device in which a plurality of bonding pads arranged on a chip and a plurality of corresponding bonding areas arranged outside the chip are respectively connected by bonding wires. A semiconductor device characterized in that, with respect to a bonding wire led out from one bonding pad to a bonding area, a corner portion of another bonding pad adjacent thereto facing the bonding wire is shaved off. 2. Claim 1, in which the shaved surface of the corner of the bonding pad is parallel to the bonding wire facing thereto.
1. Semiconductor device described in Section 1. 3. The semiconductor device according to claim 1, wherein the shaved surface of the corner of the bonding pad forms an angle of 45 degrees with each side of the bonding pad.