JPS62109248U - - Google Patents
Info
- Publication number
- JPS62109248U JPS62109248U JP20000185U JP20000185U JPS62109248U JP S62109248 U JPS62109248 U JP S62109248U JP 20000185 U JP20000185 U JP 20000185U JP 20000185 U JP20000185 U JP 20000185U JP S62109248 U JPS62109248 U JP S62109248U
- Authority
- JP
- Japan
- Prior art keywords
- central processing
- processing unit
- interface circuit
- microcomputer
- system evaluation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000011156 evaluation Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 4
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
- Microcomputers (AREA)
Description
第１図は、本考案を実施したマイクロコンピユ
ータ・システム評価装置と、マイクロ・コンピユ
ータ・システムとを接続した構成図である。第２
図、第３図および第４図は、本考案のインタフエ
ース回路の実施例を示す図である。第５図は、マ
イクロ・コンピユータ・システム内に中央処理部
を実装した基板の構成図である。第６図は、従来
のインターフエース回路図の例である。第７図は
、中央処理部と周辺回路との間の信号の時間と電
圧の関係図である。
１……マイクロ・コンピユータ・システム評価
用基板、２……中央処理部、３……インタフエー
ス回路、４……ケーブル、５……マイクロ・コン
ピユータ・システム基板、６……ソケツト、７，
８，１０，１１，１２，１３，１４，１５，１６
……インタフエース回路例、９……切り換え部、
１７……中央処理部がマイクロ・コンピユータ・
システム基板に組みこまれている場合の中央処理
部と周辺回路との間の信号の時間―電圧特性、１
８……マイクロ・コンピユータ・システム評価用
基板内の中央処理部とケーブルを直接接続した場
合の、中央処理部と周辺回路との間の信号の時間
―電圧特性、１９……マイクロ・コンピユータ・
システム評価用基板内に中央処理部とケーブルの
間の抵抗を入れた場合の、中央処理部と周辺回路
との間の信号の時間―電圧特性、２０……スレツ
シユホルド電圧、２１……スレツシユホルド電圧
を越れた時刻。
FIG. 1 is a configuration diagram in which a microcomputer system evaluation device implementing the present invention is connected to a microcomputer system. Second
3 and 4 are diagrams showing embodiments of the interface circuit of the present invention. FIG. 5 is a block diagram of a board on which a central processing section is mounted within a microcomputer system. FIG. 6 is an example of a conventional interface circuit diagram. FIG. 7 is a diagram showing the relationship between time and voltage of signals between the central processing unit and peripheral circuits. DESCRIPTION OF SYMBOLS 1...Micro computer system evaluation board, 2...Central processing unit, 3...Interface circuit, 4...Cable, 5...Micro computer system board, 6...Socket, 7,
8, 10, 11, 12, 13, 14, 15, 16
...Interface circuit example, 9...Switching section,
17...The central processing unit is a microcomputer.
Time-voltage characteristics of signals between the central processing unit and peripheral circuits when built into a system board, 1
8...Time-voltage characteristics of the signal between the central processing unit and the peripheral circuit when the cable is directly connected to the central processing unit in the microcomputer system evaluation board, 19...Microcomputer system evaluation board
Time-voltage characteristics of the signal between the central processing unit and the peripheral circuit when a resistor is inserted between the central processing unit and the cable in the system evaluation board, 20...Threshold voltage, 21...Threshold voltage The time passed.
Claims (1)
イクロ・コンピユータ・システムの評価用として
用いられるマイクロ・コンピユータ・システム評
価装置において、マイクロ・コンピユータ・シス
テムとマイクロ・コンピユータ・システム評価装
置との間に電気的接続条件の異なる複数の接続回
路を有し、前記複数の接続回路を選択できること
を特徴とするインタフエース回路。 The present invention is a microcomputer system evaluation device used for evaluating microcomputer systems that are under development or have completed development. An interface circuit comprising a plurality of connection circuits with different connection conditions, the plurality of connection circuits being selectable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20000185U JPS62109248U (en) | 1985-12-25 | 1985-12-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20000185U JPS62109248U (en) | 1985-12-25 | 1985-12-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62109248U true JPS62109248U (en) | 1987-07-11 |
Family
ID=31162149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20000185U Pending JPS62109248U (en) | 1985-12-25 | 1985-12-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62109248U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07202620A (en) * | 1993-12-29 | 1995-08-04 | Nec Corp | Signal output circuit |
-
1985
- 1985-12-25 JP JP20000185U patent/JPS62109248U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07202620A (en) * | 1993-12-29 | 1995-08-04 | Nec Corp | Signal output circuit |
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