JPS62108578A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62108578A
JPS62108578A JP24861785A JP24861785A JPS62108578A JP S62108578 A JPS62108578 A JP S62108578A JP 24861785 A JP24861785 A JP 24861785A JP 24861785 A JP24861785 A JP 24861785A JP S62108578 A JPS62108578 A JP S62108578A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
impurity
concentration layer
impurity regions
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24861785A
Other languages
Japanese (ja)
Inventor
Masayoshi Akiyama
秋山 政由
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP24861785A priority Critical patent/JPS62108578A/en
Publication of JPS62108578A publication Critical patent/JPS62108578A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce leakage currents by forming a groove to an insulating film on the surface of a semiconductor substrate among a plurality of diodes and exposing the surface of the semiconductor substrate. CONSTITUTION:The surface section of a semiconductor substrate 11 is oxidized and coated with an silicon dioxide film 14, and a P-type impurity such as boron is introduced to the surface section of the substrate 11 from windows bored to the silicon dioxide film 14 to shape impurity regions 15, 16. The N-type semiconductor substrate 11 and the P-type impurity regions 15, 6 each constitute diodes, and anode electrodes 17, 18 are brought into contact with the impurity regions 15, 16. On the other hand, a back metal as a common cathode electrode 19 is laminated on a high impurity concentration layer 12. An approximately V-shaped groove 20 reaching up to the high impurity layer 12 is shaped to the silicon dioxide film 14 between the impurity regions 15 and 16, and a low impurity concentration layer 13. Accordingly, a path for leakage currents flowing on the interface between the insulating film and the semiconductor substrate is interrupted by the groove, thus reducing leakage currents between the impurity regions.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は半導体装置に係わり、特に、単一の半導体基板
に形成された複数のダイオード間の漏洩電流を防止した
半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor device, and particularly to a semiconductor device that prevents leakage current between a plurality of diodes formed on a single semiconductor substrate.

〈従来の技術〉 第3図は従来の半導体装置を示す断面図であり、1は、
高不純物濃度層2と低不純物濃度層3とから成るn型の
半導体基板を示している。この半導体基板1の表面部は
酸化されて二酸化シリコン膜4で被われており、この二
酸化シリコン膜4に穿設された窓から基板1の表面部に
p型の不純物、例えばボロンが導入されて不純物領域5
,6が形成されている。n型の半導体基板1とp型の不
純物領域5,6とはそれぞれダイオードを構成しており
、不純物領域5,6とにはアノード電極7゜8が接触し
ている。一方、高不純物濃度層2には共通カソード電極
9としての裏メタルが積層されている。
<Prior art> FIG. 3 is a sectional view showing a conventional semiconductor device, and 1 is a sectional view showing a conventional semiconductor device.
An n-type semiconductor substrate consisting of a high impurity concentration layer 2 and a low impurity concentration layer 3 is shown. The surface of the semiconductor substrate 1 is oxidized and covered with a silicon dioxide film 4, and a p-type impurity such as boron is introduced into the surface of the substrate 1 through a window formed in the silicon dioxide film 4. Impurity region 5
, 6 are formed. The n-type semiconductor substrate 1 and the p-type impurity regions 5 and 6 each constitute a diode, and the anode electrode 7.8 is in contact with the impurity regions 5 and 6. On the other hand, a back metal serving as a common cathode electrode 9 is laminated on the high impurity concentration layer 2 .

かかる構造の半導体装置は、アノード電極7゜8と共通
カソード電極9との間に電流をそれぞれ流し、所謂ツイ
ンダイオードとして機能する。
A semiconductor device having such a structure allows current to flow between the anode electrode 7.8 and the common cathode electrode 9, respectively, and functions as a so-called twin diode.

〈発明の解決しようとする問題点〉 上記従来の半導体装置にあっては、製造工程中の僅かな
汚染等により二酸化シリコン膜4と半導体基板1との界
面状態が悪くなり、該界面を伝わって不純物領域5と不
純物領域6との間に漏洩電流が流れていた。
<Problems to be Solved by the Invention> In the conventional semiconductor device described above, the state of the interface between the silicon dioxide film 4 and the semiconductor substrate 1 deteriorates due to slight contamination during the manufacturing process, and contaminants propagate through the interface. A leakage current was flowing between impurity region 5 and impurity region 6.

加えて、不純物領域5,6は低不純物濃度層3内に形成
されているので、不純物領域5と低不純物濃度層3と不
純物領域6とで寄生バイポーラトランジスタが形成され
るので、アノード電極7に印加される電圧がカソード電
極9はもとより、アノード電極8よりも高くなると寄生
バイポーラトランジスタが順方向にバイアスされてアノ
ード電極7.8間に漏洩電流が流れていた。
In addition, since the impurity regions 5 and 6 are formed within the low impurity concentration layer 3, a parasitic bipolar transistor is formed by the impurity region 5, the low impurity concentration layer 3, and the impurity region 6. When the applied voltage was higher than the anode electrode 8 as well as the cathode electrode 9, the parasitic bipolar transistor was biased in the forward direction, and a leakage current was flowing between the anode electrodes 7 and 8.

かかる界面を流れる電流と寄生バイポーラトランジスタ
による電流とは、1乃至100μA程度であるものの、
かかる僅かの漏洩電流も高精度を要求される電子回路で
はさらに減少させることが要求されており、漏洩電流の
減少が複数のダイオードを単一基板に集積した半導体装
置の問題点となっていた。
Although the current flowing through such an interface and the current due to the parasitic bipolar transistor is about 1 to 100 μA,
Electronic circuits that require high precision are required to further reduce such a small amount of leakage current, and reducing leakage current has been a problem with semiconductor devices in which a plurality of diodes are integrated on a single substrate.

従って、本発明は漏洩電流をさらに減少させた複数のダ
イオードから成る半導体装置を提供することを目的とし
ている。
Therefore, it is an object of the present invention to provide a semiconductor device comprising a plurality of diodes with further reduced leakage current.

〈問題点を解決するための手段〉 本発明は、第1導電型の高不純物濃度層に第1導電型の
低不純物濃度層を重畳した単一の半導体基板の表面に絶
縁膜を成長させ該絶縁膜下の半導体基板の表面部に複数
の第2導電型の不純物領域を形成し前記半導体基板と前
記複数の不純物領域とで複数のダイオードをそれぞれ形
成した半導体装置において、前記複数のダイオード間の
半導体基板表面の絶縁膜に溝を形成し前記半導体基板の
表面を露出させることにより、半導体基板と絶縁膜との
界面の影響を除去したことを要旨とする。
<Means for Solving the Problems> The present invention involves growing an insulating film on the surface of a single semiconductor substrate in which a first conductivity type high impurity concentration layer and a first conductivity type low impurity concentration layer are superimposed. In a semiconductor device in which a plurality of impurity regions of a second conductivity type are formed in a surface portion of a semiconductor substrate under an insulating film, and a plurality of diodes are respectively formed by the semiconductor substrate and the plurality of impurity regions, The gist of this invention is to eliminate the influence of the interface between the semiconductor substrate and the insulating film by forming a groove in the insulating film on the surface of the semiconductor substrate and exposing the surface of the semiconductor substrate.

〈実施例〉 第1図および第2図は本発明の第1実施例を示す図であ
り、本発明を高周波用ダイオード装置に適用した例を示
している0図において、11は、高不純物濃度層12と
低不純物濃度層13とから成るn型の半導体基板を示し
ている。この半導体基板11の表面部は酸化されて二酸
化シリコン膜14で被われており、この二酸化シリコン
膜14に穿設された窓から基板11の表面部にp型の不
純物、例えばボロンが導入されて不純物領域15゜16
が形成されている。n型の半導体基板11とp型の不純
物領域15.16とはそれぞれダイオードを構成してお
り、不純物領域15.16とにはアノード電極17.1
8が接触している。一方、高不純物濃度層12には共通
カソード電極19としての裏メタルが積層されている。
<Example> FIGS. 1 and 2 are diagrams showing a first example of the present invention. In FIG. An n-type semiconductor substrate consisting of a layer 12 and a low impurity concentration layer 13 is shown. The surface of the semiconductor substrate 11 is oxidized and covered with a silicon dioxide film 14, and a p-type impurity such as boron is introduced into the surface of the substrate 11 through a window formed in the silicon dioxide film 14. Impurity region 15°16
is formed. The n-type semiconductor substrate 11 and the p-type impurity region 15.16 each constitute a diode, and the impurity region 15.16 is connected to an anode electrode 17.1.
8 are in contact. On the other hand, a back metal serving as a common cathode electrode 19 is laminated on the high impurity concentration layer 12 .

前述の不純物領域15と16との間の二酸化シリコン膜
14と低不純物濃度層13とには高不純物層12まで達
する略V字形の溝20が形成されており、この略V字形
の溝20は、カッタ等による物理的方法。
A substantially V-shaped groove 20 reaching up to the high impurity layer 12 is formed in the silicon dioxide film 14 and the low impurity concentration layer 13 between the impurity regions 15 and 16 described above. , a physical method by Cutter et al.

エツチング等の化学的方法あるいはレーザ等による光学
的方法のいずれにより形成してもよい。
It may be formed by either a chemical method such as etching or an optical method using a laser or the like.

かかるV字形の溝20を有する半導体装置にあっては、
二酸化シリコン膜14と半導体基板11との界面が不純
物領域5,6間で切断されているので、この界面を流れ
る漏洩電流を防止できる上、寄生トランジスタは構成さ
れないので、寄生トランジスタによる漏洩電流も防止で
きる。事実、7字形の溝20を有するツインダイオード
装置では、漏洩電流を数十nAに減少させることができ
た。
In a semiconductor device having such a V-shaped groove 20,
Since the interface between silicon dioxide film 14 and semiconductor substrate 11 is cut between impurity regions 5 and 6, leakage current flowing through this interface can be prevented, and since no parasitic transistor is formed, leakage current due to parasitic transistors can also be prevented. can. In fact, the twin diode device with the figure 7 groove 20 was able to reduce the leakage current to a few tens of nA.

〈効果〉 以上説明してきたように、この発明によれば、絶a膜と
半導体基板との界面を流れる漏洩電流経路を絶縁膜に形
成された溝で遮断したので、不純物領域間の漏洩電流を
減少させることができるという効果が得られる。
<Effects> As explained above, according to the present invention, the leakage current path flowing through the interface between the absolute film and the semiconductor substrate is blocked by the groove formed in the insulating film, so that the leakage current between the impurity regions can be reduced. The effect is that it can be reduced.

さらに、一実施例では低不純物濃度層にも溝を形成した
ので、界面を流れる漏洩電流だけでなく、寄生トランジ
スタによる漏洩電流も防止することができ不純物領域間
の漏洩電流を極めて僅かにすることができるという利点
を有する。
Furthermore, in one embodiment, grooves are formed in the low impurity concentration layer, so that not only leakage current flowing through the interface but also leakage current due to parasitic transistors can be prevented, and leakage current between impurity regions can be extremely minimized. It has the advantage of being able to

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を表わす断面図、第2図は第
1図に示された半導体装置の平面図、第3図は従来例の
を示す断面図である。 11・・・・・・・半導体基板。 12・・・・・・・高不純物濃度層。 13・・・・・・・低不純物濃度層、 14・・・・・・・絶縁膜、 15.16・・・・不純物領域 2o・・・・・・・溝。 特許出願人      ローム株式会社代理人   弁
理士  桑 井 清 −第1図 第2図 ソ 第3図
FIG. 1 is a sectional view showing one embodiment of the present invention, FIG. 2 is a plan view of the semiconductor device shown in FIG. 1, and FIG. 3 is a sectional view of a conventional example. 11... Semiconductor substrate. 12...High impurity concentration layer. 13...Low impurity concentration layer, 14...Insulating film, 15.16...Impurity region 2o...Groove. Patent Applicant: ROHM Co., Ltd. Agent, Patent Attorney Kiyoshi Kuwai - Figure 1, Figure 2, Figure 3

Claims (2)

【特許請求の範囲】[Claims] (1)第1導電型の高不純物濃度層に第1導電型の低不
純物濃度層を重畳した単一の半導体基板の表面に絶縁膜
を成長させ該絶縁膜下の半導体基板の表面部に複数の第
2導電型の不純物領域を形成し前記半導体基板と前記複
数の不純物領域とで複数のダイオードをそれぞれ形成し
た半導体装置において、前記複数のダイオード間の半導
体基板表面の絶縁膜に溝を形成し前記半導体基板の表面
を露出させたことを特徴とする半導体装置。
(1) An insulating film is grown on the surface of a single semiconductor substrate in which a first conductivity type high impurity concentration layer and a first conductivity type low impurity concentration layer are superimposed, and a plurality of insulating films are grown on the surface of the semiconductor substrate under the insulating film. In the semiconductor device in which a second conductivity type impurity region is formed, and a plurality of diodes are respectively formed in the semiconductor substrate and the plurality of impurity regions, a groove is formed in an insulating film on a surface of the semiconductor substrate between the plurality of diodes. A semiconductor device characterized in that a surface of the semiconductor substrate is exposed.
(2)前記低不純物濃度層に前記絶縁膜に形成された溝
と連続する溝を形成し高不純物濃度層を露出させた特許
請求の範囲第1項記載の半導体装置。
(2) The semiconductor device according to claim 1, wherein a groove continuous with a groove formed in the insulating film is formed in the low impurity concentration layer to expose the high impurity concentration layer.
JP24861785A 1985-11-06 1985-11-06 Semiconductor device Pending JPS62108578A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24861785A JPS62108578A (en) 1985-11-06 1985-11-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24861785A JPS62108578A (en) 1985-11-06 1985-11-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62108578A true JPS62108578A (en) 1987-05-19

Family

ID=17180778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24861785A Pending JPS62108578A (en) 1985-11-06 1985-11-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62108578A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008186920A (en) * 2007-01-29 2008-08-14 Mitsubishi Electric Corp Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56144174A (en) * 1980-04-11 1981-11-10 Matsushita Electric Ind Co Ltd Diode array
JPS59121882A (en) * 1982-12-28 1984-07-14 Toshiba Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56144174A (en) * 1980-04-11 1981-11-10 Matsushita Electric Ind Co Ltd Diode array
JPS59121882A (en) * 1982-12-28 1984-07-14 Toshiba Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008186920A (en) * 2007-01-29 2008-08-14 Mitsubishi Electric Corp Semiconductor device

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