JPS62105241A - Sequence controller for data processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) This invention relates to controlling the sequence in which multiple tasks are processed by a data processor.

It is desirable to process the highest priority tasks and minimize the overhead due to task sequencing.

SUMMARY OF THE INVENTION A general feature of the invention is to store queues, each containing information identifying pending tasks of a particular priority, and to identify the highest priority queue that is not free. The task is to maintain queue occupancy data that can be processed and access queue storage based on the queue occupancy data to find the highest priority pending task and designate it as the next task to be processed.

A preferred embodiment of the invention includes the following features.

The occupancy data is a bitmap whose successive bits represent the free or non-free status of the corresponding queue, and the bitmap is applied to the queue address table to determine the highest priority non-free queue address. It will be done. The queues corresponding to successive bits of the bitmap are ordered by priority. The lowest priority queue always contains only background tasks, and its corresponding bit in the bitmap is always the value of the free queue.

The task is stored at the assigned address in the task store. Each queue maintains the task address of the oldest pending task in that queue, and the task store also maintains a link to each task representing the next most recent pending task in that queue. The queue also holds the address of the latest pending task. If there are no tasks pending for a queue, the queue holds a value of zero.

The queue address spans multiple locations in the bitmap table, and the bitmap is an offset address that can only take even values.

The queue is updated after each task is executed.

Tasks are processed on a priority basis, and the overhead required to update the bitmap and apply it to the encoder table is extremely small.

Other advantages and features will be apparent from the following description of the preferred embodiments and from the claims.

Structure In FIG. 1, a task processor 10 includes a task store 12 that holds task control blocks 14 of a current set of tasks to be executed by a task executor 15, pending execution. The set of tasks changes over time as tasks are executed and new tasks are ready for execution. Each task is pre-assigned a priority so that higher priority tasks are always executed before lower priority tasks. Tasks with the same priority are to be executed in a first-in first-out order.

In the task storage device 12, each task control block 14
is stored in one address 16. Each task control block stores information specifying the position in the first-in/first-out order of tasks within a certain priority level. This information is in the form of a link 18, which is the address (in storage 12) of the task control block of the next pending task of the same priority awaiting processing. If there is none, the value of link 18 is zero. Each task control block consists of a concatenation 21 (containing the address in task memory (not shown) of the task's next command to be executed) and a priority byte 23 (an 8-bit byte that specifies the task's priority as described below). (displayed in a certain manner).

Generally, when the task executor 15 stops executing a task, the task executor 15 sends a task completion signal 19 to the next task address generator 20.

Then, the generator 20 issues the task control block (TCB) address 22 of the next task to the task switch 25. Therefore, the task switch 25 selects TCB address 2.
2 to the storage device 22 and the task control block 14
seek. Address generator 20 stores a set of queues. One queue is for each priority. Each queue contains in task store 12 the TCB addresses of first-in and last-in pending tasks for that priority.

In FIG. 2, eight different priority queues 30 are shown (numbered 0-7, with 7 being the highest priority), each queue being stored at a queue address 32, with the first The task storage for pending tasks in and last in, 12), contains two TCB addresses 34 and 36. If no task of a particular priority is waiting to be executed, its queue contains the value zero (e.g., the queue at address QB in Figure 2); when there is only one task of a particular priority; That address appears in addresses 34 and 36 of first-in and last-in tasks (for example, task Q in a queue with priority 5).Hereafter, a queue with a specific priority, for example 5, will be simply referred to as queue 5. Make it. T of the current task being executed by the task executor 15 at a given time
The CB address is located in the highest priority queue that does not contain zero (ie, is not free). There is always at least one task in the task store 12 (referred to as a background task). Queue O is the TCB of the background task
Always include the address, and only that.

Returning again to FIG. 1, the level byte 23 of each control block 14 indicates the priority of the task by a single value of 8 and 0 in one bit position within the byte l-, e.g., level byte 0000100 indicates priority. Showing the second degree task.

Generator 20 uses the bitmap to keep track of the empty or non-empty status of the various queues, and this is done in the following manner.

In FIG. 3, there are eight locations in bitmap 50 that correspond in turn to eight different queues.

-i, a given p1~position has a value of zero if the queue is empty, and a value of one if it is not. That is, the highest value of 1 in the bitmap indicates the highest priority queue containing the task address of the task waiting to be executed. In the particular bitmap 50 shown in FIG. 3, the value 1 at location 7 indicates that queue 7 is the highest priority queue containing the addresses of pending tasks.

Since queue 0 is always occupied by a background task, the low order bit of any bitmap will have the value 1 under the -m rule described above. However, as can be seen from Figure 3, the lower bits are always arbitrarily set to the value zero (for reasons that will become clear below), which means that there are 128 different values that the bitmap can take. .

The bitmap is formed by performing an OR operation on the level bytes of all tasks waiting to be executed. To ensure that the low-order bits of the bitmap are always zero, the background task's level byte is set to oo
It is set to ooooo.

Referring to FIG. 4, priority encoder table 60
(stored in generator 20 of FIG. 1),
For example, in FIGS. 2 and 3, bitmap 50 (FIG. 4) has a pending task. It is converted to the address QA of queue 7, which is the queue with the highest priority. The ff precedence encoder table 60 contains multiple copies of each queue address (except for queue 0 addresses and queue 1 addresses). For example, it has 04 copies of address QA, which represents a low priority binding number. In other words, there are 64 possible combinations of a zero queue and an occupied queue of lower priority than queue 7, but as long as queue 7 is occupied, the queue address is 6.
Must be QA in all four cases.

To explain FIG. 5, the next task address generator 2
0, the priority encoder table 60 is the queue specifier 6
A bitmap representing the current occupancy state of the 9 queues 30, which are part of
is provided to a priority encoder table 60 by a bitmap generator 66 that is part of the encoder table 60. The bitmap 50 is used as an offset address added to the base address of the priority encoder table 60, i.e. as the address 67 of the location where the first queue address entry 32 appears, to obtain the proper location in the priority encoder table 60. used. In encoder table 60, each cue atto occupies two consecutive byte locations.

The first byte of successive addresses is placed at each odd successive offset address.

As mentioned above, the lowest priority bit of a bitmap is always set to zero, so the bitmap is
If desired, odd-valued offset addresses will always be represented.

-Finally, the bitmap generator 66 determines the bitmap 50 based on the priority byte 70 received from the queue updater 72; The queue updater 72 receives the task completion signal 1
9 or the next task control block address (representing the TCI+address of the next task that is ready for execution), updates the queue stored in queue storage 74.

Queue store 74 receives each current queue address 32 from priority encoder table 60 and stores its corresponding T
Outputs CP address 22.

Specifically, each time the task completion signal 19 arrives, the queue updater 72 learns whether another task with the same priority is waiting to be executed. This is determined by checking the link field in the TCB of the task that just completed. If a task with the same priority is waiting to execute, the link contains the TCB address of the next task.
The TCB address is sent to the task switch 25. Switcher 25 applies this TCB address to storage device 12 to obtain a task control block. Then, the task switch 25 starts executing the task using the task control block.

If there is no other task waiting to execute with the same priority as the just completed task, ie, the link field of the TCB of the just completed task is zero, then the bitmag must be updated.

To accomplish this, the queue updater sends to bitmap generator 66 the priority byte of the task that just completed. The value 1 bit of this priority byte is theoretically removed from the bitmap by bitmap generator 66. The revised bitmap is sent to priority encoder table 60 to enforce the new highest priority queue.

Each time one task completion signal appears, the queue updater 72
6. Determine the link from the task that just completed and use it in place of the first-in-task control block address of the appropriate queue.

When a task is first ready for execution, its task control block address comes to queue updater 72. The queue updater uses the TCB address to update the priority of the new task from the task control block storage 12.
seek. The queue updater transfers the priority by 1- to line 7.
9 to the priority encoder table 60 to determine the address of the queue to be updated. The address is applied to queue storage 74 to determine whether the queue is free. If it is empty, queue updater 7
2 updates the first-in and last-in entries in the queue table to hold the TCB address of the new task. If it is not empty, the queue updater 72 updates only the last-in address and updates the TC of the new task.
Insert the B address into the previous zero link of the previous last-in task. The queue updater also ORs the priority byte with its copy of the bitmap to determine whether the p1-map is changed to the p1-map of the new highest priority queue. If changed, the new task is the highest priority task. Therefore, the queue updater transfers the TCB address 22 to the task switcher 25.
have it sent to The task switcher 25 then interrupts execution of the current task and begins execution of a new task.

In operation, when a task is ready for execution, the queue updater updates the links and queues appropriately. Tasks are identified for execution one after another such that at a given time the first-in highest priority task is the task selected for execution. A bitmap representing queue storage occupancy is applied to the priority encoder table. The priority encoder table outputs the required queue addresses. After each task finishes, the bitmap is updated and the next task address is determined from the priority encoder table.

The bitmap and priority encoder table allow the next task to be directed quickly with minimal overhead.

Other embodiments are within the scope of the claims.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a task processor in this invention. FIG. 2 is a table of queues. FIG. 3 is a bitmap. FIG. 4 is a priority encoder table. FIG. 5 is a block diagram of the next task address generator of FIG. (5 others) Drawing NγC <No change in content); Fig 2 /゛' Procedural amendment Re-Patent Application No. 215570 of 1988 2) Name of the invention Sequence control device for data processor 3, amended Relationship with the Patent Case Patent Applicant Address Name Codex Corporation 4, Agent Address 2-2 Otemachi, Chiyoda-ku, Tokyo? #1 No. 5,
Target of correction

Claims (11)

[Claims] (1) A control device for controlling the execution sequence of multiple tasks in a data processor by specifying the next task to be processed from among a plurality of pending tasks waiting to be processed. , each of said tasks having a predetermined priority for processing in a different priority order, each associated with said different priority, and identifying pending tasks with said associated priority; a queue storage device for storing a plurality of queues containing information; means for maintaining queue occupancy data identifying a queue that has the highest priority and is not free; A control device comprising: means for accessing and discovering the highest priority pending task; (2) In the control device according to claim 1,
The occupancy data comprises a bitmap having a series of bits each representing the free or non-free state of the corresponding queue, and the means for accessing each one of the queues in the queue storage device. A control device comprising: a table of entries which are queue addresses of queue addresses; and means for applying said bitmap to said table to determine the queue address of the highest priority non-empty queue. (3) In the control device according to claim 1,
A control device characterized in that the occupancy data includes a series of bits each representing an empty state or a non-empty state of the corresponding queue. (4) A control device according to claim 2 or 3, wherein the queues corresponding to successive bits are arranged in the order of priority. (5) In the control device according to claim 2 or 3, one of the queues always includes a background task;
A control device characterized in that the bit corresponding to the one queue is always set to a value different from a value representing a non-empty queue. (6) In the control device according to claim 5,
A control device characterized in that the one queue is a queue with the lowest priority and includes only the background task. (7) In the control device according to claim 1,
further comprising a task store for holding each of said tasks at an assigned task address, said queue store storing, with respect to each of said queues, a task of the oldest pending task having a priority of said queue; A control device having an address and wherein said task store has, for each said task, a link representing the task address of the next most recent pending task for that queue. (8) In the control device according to claim 7,
A control device characterized in that the queue storage further holds a task address of the latest pending task. (9) In the control device according to claim 8,
A control device characterized in that the queue storage device holds a value of zero for any queue that has no pending tasks. (10) In the control device according to claim 2, each of the queues is stored in the queue storage device at a queue address, the queue address spans a plurality of locations in the table, and the bitmap is odd. A control device characterized in that the offset address has only numerical values. (11) The control device according to claim 1, further comprising a queue updater for updating information in the queue after each of the tasks is executed.