JPS62105055A - Analog mean value circuit - Google Patents

Abstract

PURPOSE:To prevent an abnormal output voltage from being generated when an input voltage is disconnected by providing a parallel circuit consisting of switches and resistors connected in series with plural input terminals where an analog voltage is applied. CONSTITUTION:The output terminal 10 of the parallel circuit composed of a switch 4 and a resistance 7, a switch 5 and a resistance 8, and a switch 6 and a resistance 9 is connected to the uninverted input terminal 22 of an operational amplifier 20, and the output terminal 23 of the operational amplifier 20 is connected to the inverted input terminal 21 to form a feedback circuit. The resistance value of the respective resistors 7-9 is denoted as R. Then when input voltages V1-V3 are applied to respective input terminals 1-3, an output voltage V40 developed at the circuit output terminal 40 is as shown by equation I because the input impedance of the amplifier 20 is high, and the voltage V40 is equal to the mean value of the voltages V1-V3. When one switch, e.g. 4 is opened to disconnect the voltage V1, the voltage V40 is as shown by equation II. Namely, the voltage V40 is switched to the mean value of the voltages V2 and V3 immediately with only one switch 4. Therefore, the voltage V40 never becomes abnormal in the middle.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an analog average value circuit used in measuring devices and stationary devices to calculate the average value of a plurality of analog voltages. This invention relates to an analog average value circuit in which it is easy to separate the voltage applied.

[Prior Art] FIG. 2 is a circuit diagram showing a conventional analog average value circuit with a disconnection function. In the figure, (1), (2), (3
) are the input terminals to which analog voltage is applied, respectively, (
4), (5), and (6) are input voltage disconnection switches connected to each input terminal (1) to <3), respectively, and (7), (8), and ku) are Each switch (4
) to (6), one resistor connected to each input terminal (1) to (3), and switch (4).
-(6) and resistors (7)-(9) form three series input circuits connected correspondingly, and the other ends of resistors (7)-(9) are connected together. This serves as an output terminal (10) and constitutes one parallel circuit. (2
0) is an operational amplifier whose inverting input terminal (21) is connected to the output terminal (10) of the parallel circuit, and its non-inverting input terminal (22) is connected to a circuit not shown. (2
4), (25), and (26) are resistors connected in parallel between the inverting input terminal (21) and the output terminal (23) of the operational amplifier (20), respectively, and (27), (28) ,(
29) is connected to each resistor (24) to (26) and the output terminal (23).
), and (30) is a circuit output terminal drawn out from the output terminal (23) of the operational amplifier (20).

In this example, when the resistance values of resistors (7) to (9) are respectively R, the resistance values of resistors (24) to (26) are R/3, R/2, and R, respectively. Assume that it is selected as follows.

The conventional analog average value circuit is configured as described above, and as shown in Figure 2, there is a switch for disconnecting the input voltage (
4) to (5) and the gain switching switch (27) are closed, and the other gain switching switches (28), (
29) is open, each input terminal (1) to (3
), respectively, the output voltage v3b at the circuit output terminal (3o) is.

V30= [(V+/R)”(Vt/R)”(Vz/
R)]・R/3=-(V++V2+Vs)/3'
"'■.From the formula (■), it can be seen that the output voltage V, . is the average value of the input voltages (1), (2), and v, although the sign is reversed.

Here, if you want to disconnect one of the input voltages V7, v2, and V, for example, the input voltage vI, use the input terminal (1).
The input voltage disconnection switch (4) connected to is opened, and at the same time, the gain switching switch (2) is opened and the switch (28) is closed. The output voltage v3° at this time is V30=-[(Vt/R)+(V3/R)1-R/2
=-(V2+V3)/2 The river becomes ■. ■Output voltage Vl from the formula. is the average value of the input voltage V8, v. For example, if one input voltage V1
It can be seen that even when the input voltages v2 and v5 are separated, the average value of the remaining input voltages v2 and v5 is maintained.

[Problems to be solved by the invention] In conventional analog average value circuits, for example, input type,
JEV“e6]')!11th %L:Jl'i
&ty＞x4°″ゝ・3′″ゝ: Since and (28) are switched at the same time, their □, ti f′e″″s f(′″') tl
< L tiltrljfl (7) 扛”1°7°゛1
Temporarily output voltage V,. There is a problem that the output voltage value becomes an abnormal value, and since the switching time difference is particularly large in mechanical switches, there are problems such as the need to temporarily store the output voltage value to avoid this problem. Ta.

This invention was made to solve the above problems, and it provides an analog average value circuit that can reliably prevent the occurrence of abnormal output voltage when the input voltage is disconnected without storing the output voltage value. The purpose is to obtain.

[Means for Solving the Problems] The analog average value circuit according to the present invention includes a parallel circuit consisting of a switch and a resistor connected in series to each of a plurality of input terminals to which an analog voltage is applied, and this parallel circuit. and a high input impedance operational amplifier connected to the output terminal of the amplifier.

[Function] In this invention, when the input voltage is disconnected, by operating only one switch, the average value of the plurality of analog voltages applied to the remaining input terminals of the parallel circuit can be immediately switched without producing an abnormal output voltage. Output.

[Embodiment FP4] An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a circuit diagram showing an embodiment of the present invention, and (1) to (
10) and (20) to (23) are similar to the conventional circuit described above, and (40) corresponds to the circuit output terminal (3o). In Figure 1, the operational amplifier (2o) has a high input impedance, and the non-inverting input terminal (22) of the operational amplifier (20) is connected to the output terminal (10) of the parallel circuit.
) is connected to the inverting input terminal (21), and an operational amplifier (
20) is connected to the output terminal (23) to form a feedback circuit. Further, the resistance value of each resistor (7) to (9) is assumed to be R as described above.

Next, the operation of the embodiment of the invention shown in FIG. 1 will be explained. When input voltages ■1, ■2, ■ are applied to each input terminal (1) to (3), respectively, operational amplification of 2% (
20) is sufficiently high, the output voltage V4° appearing at the circuit output terminal (40) is V, , -
[(1/R,)/<3/R)] −V, + [(1/R,)
R)/(3/R)] -V2+ [(1/R)/(3
/R)]・■ri= (V + + V 2 + V 3
) / 3...■, and as is clear from the formula, the output voltage is ■,. is the average value of the input voltages ■, ~■,.

Here, if one switch, for example (4), is opened to disconnect the input voltage v1, the output voltage V. is V4. = [
(1/R>/(2/R) co・Vz + [(1/R)/
(2/R)] ・■z=(V2+Vj)/2
... becomes ■. That is, by operating only one switch (4) without operating a plurality of switches, the output voltage can be immediately changed. can be made the average value of the input voltage V2, ■. Therefore, the output voltage V,. does not take an abnormal value midway through the process.This also applies to the case where a switch is closed when a disconnected input voltage is added.

In the above embodiment, the case where three input voltages are handled is explained as an example, but by setting the input terminals appropriately, the number of input voltages can be set to the official level, and the number of input voltages to be disconnected can also be reduced to one. Needless to say, the number of inputs is not limited to the number of inputs, and can be arbitrarily selected as long as it is less than the total number of inputs.

Further, the circuit configuration shown in FIG. 1 can be used not only as a simple average calculation circuit, but also as a load calculation circuit, for example. In that case, the resistance value of each resistor (7) to (9) is set to R
1, R2, R, closing, V,, =): (Vi/Ri)/
The relationship Σ(1/r(i) −■(i=1~3) can be used. From the formula ■, the output voltage V, is (
It can be seen that this is a weighted average value with 1/Ri) as the weighting coefficient.

Further, in the embodiment of FIG. 1, the operational amplifier (20) has a gain of 1.
It is used as a feedback amplifier, but it is also possible to have a gain of 1 or more by using the feedback circuit as a voltage divider circuit.
This case can also be considered to be within the scope of the present invention since the same effects as described above can be obtained.

Furthermore, the circuit configuration shown in FIG. 1 has the effect of providing stability against failures of the resistors 7) to (9) in the parallel circuit.

[Effects of the Invention] As described above, according to the present invention, there is provided a parallel circuit including a switch and a resistor connected in series to each of a plurality of input terminals to which an analog voltage is applied, and a parallel circuit connected to an output terminal of the parallel circuit. Since it is equipped with an operational amplifier with a high input impedance, and one input voltage can be disconnected or combined with one switch operation, it is possible to prevent the inconvenience of the output voltage becoming an abnormal value in the middle of a switch operation. Further, since there is no need to use an output voltage holding circuit, an analog average value circuit with excellent stability without equivalent delay can be obtained even when incorporated into a negative feedback loop.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional analog average value circuit. (1), (2), (3)...Input terminals 4), (5)
, (6)...switches (7), (8), (9)...
Resistor (10)... Output terminal of parallel circuit (20)... Operational amplifier (21)... Inverting input terminal (22)... Non-inverting input terminal (23)... Output terminal of operational amplifier In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (5)

[Claims] (1) A parallel circuit consisting of a switch and a resistor connected in series to each of a plurality of input terminals to which an analog voltage is applied, and an operational amplifier with high input impedance connected to the output terminal of this parallel circuit, An analog average value circuit configured to output an average value of the plurality of analog voltages. (2) The output terminal of the parallel circuit is connected to the non-inverting input terminal of an operational amplifier, and the output terminal of the operational amplifier is connected to the inverting input terminal of this operational amplifier. Analog average value circuit as described. (3) The analog average value circuit according to claim 2, wherein the feedback circuit between the output terminal and the inverting input terminal of the operational amplifier is provided with a gain of 1 or more as a voltage dividing circuit. (4) The analog average value circuit according to any one of claims 1 to 3, wherein the resistance values of each resistor in the parallel circuit are equal. (5) The analog average value circuit according to any one of claims 1 to 3, wherein each resistor in the parallel circuit has a different resistance value.