JPS62102672A - Two-screen television receiver - Google Patents

Abstract

PURPOSE:To obtain preferable feeling at pattern erasure by erasing a sub-screen from one of upper/lower or right/left end of the screen gradually toward the other end in erasing the sub-screen. CONSTITUTION:When a switch 26 is turned on while a sub-screen is inserted to a prescribed region of a main screen, a counter 23 is operated to count down a vertical synchronizing signal VM of the main screen fed to a clock terminal CL from '64'. In this case, when the relation of read address RA>= count (x) is obtained in a comparator circuit 22, the comparison output goes to L and an AND gate 25 is closed. Thus, at the first field when the switch 26 is turned on, x=63 is obtained and the 64-th scanning line corresponding to RA=63 of the sub-screen is erased at first with the RA=63. Since the relation of x=62 is obtained at the next field, the 63rd scanning line is erased. Thus, one scanning line at each field is erased sequentially in the ascending order and all the sub-screen is erased for a time corresponding to the 63 fields, i.e., in nearly one sec.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a two-screen television receiver that displays two screens simultaneously on a common display surface.

[Summary of the invention]

The present invention provides a dual-screen television receiver in which when one screen is erased, the screen is erased gradually from the upper or lower edge or the left or right edge of the screen toward the opposite edge. By doing so, it is possible to obtain a favorable feeling when the screen is erased.

[Conventional technology]

Conventionally, as shown in Fig. 3, a B channel screen (
A two-screen television receiver is known in which a screen B (hereinafter referred to as a sub-screen) is reduced to, for example, one third of the size and displayed simultaneously on the main screen.

Such a two-screen receiver is provided with a switch for selecting whether or not to display the sub-screen.

[Problem that the invention seeks to solve]

In conventional two-screen TV receivers, if you operate the switch while the sub-screen is being displayed, the sub-screen disappears.
In this case, the entire sub-screen disappears instantly when the switch is operated, which is not necessarily desirable.

[Means for solving problems]

In the present invention, means is provided for creating a control signal that narrows the insertion area of the sub-screen over time, and the control signal controls the switching signal between the two video signals of the main screen and the sub-screen. ing.

[Effect]

The sub-screen is gradually erased from its edges.

〔Example〕

In FIG. 1, 1 is an antenna, 2 is a tuning circuit, 3 is an intermediate frequency amplification and video detection circuit, and 4 is a composite video signal input terminal, to which, for example, a reproduction signal of a VTR is supplied.

5 is a switching circuit for switching between the main screen and the sub-screen. The main screen signal obtained from this switching circuit 5 is Y
In addition to the /C processing and synchronization processing circuit 6, a main screen video signal SN, a main screen vertical synchronization signal 8, and a main screen horizontal synchronization signal HM are obtained. At the same time, the signal for the sub-screen obtained from the switching circuit 5 is added to the Y/C processing and synchronization processing circuit 7, and is sent to the video signal S3 for the sub-screen, the vertical synchronization signal for the sub-screen ■, and the horizontal synchronization signal for the sub-screen. H3 is obtained.

The signal S is applied to the A/D converter 8 and converted into a digital signal, and this digital signal is written into the memory 10 through the write processing circuit 9. In this case, when the sub-screen is reduced to, for example, 1/3 of the main screen, the write processing circuit 9 extracts one out of every three scanning lines and writes it into the memory 10. As a result, information on an effective screen consisting of, for example, 64 scanning lines per field is written into the memory 10.

The sub-screen clock oscillator 11 generates a clock pulse of frequency f while being synchronized with the above signals 5 and H5,
Based on this, the write address generator 12 outputs "0" to "
63'' write address generator. This address WA is supplied to the memory IO through the memory control circuit 13.

The data read from the memory IO is sent to the read processing circuit 1.
4 to the D/A converter 15 and returned to the original analog video signal S.

The main screen clock oscillator 16 uses the above signal ■. , H, generates a clock pulse of frequency fR while being synchronized with
Based on this, the read address generator 17 outputs "0" to "
A read address RA of ``63'' is generated. This address RA is supplied to the memory 10 through the memory control circuit 13. When the sub-screen is reduced to 1/3, the above-mentioned reading is performed at three times the speed of writing. That is, information for one scanning line is read out at a speed of 1/3H. Note that the above write frequencies f, I and read frequencies fll are, for example, f, 1=4/3fsc, fR, where the subcarrier frequency is rsc.
=2fsc is selected.

The signal S obtained from the D/A converter 15.

is the signal SM obtained from the processing circuit 6 to the synthesis circuit 18.
Added with. This synthetic circuit engineer 8 is a control circuit 19
from the switching signal generation circuit 21 to the AND gate 25
It is controlled by a switching signal Sc applied through. As a result, a composite signal SH+S in which the signal S is inserted into a predetermined region of the signals S and 4 is obtained from the composite circuit 18, and this signal is supplied to the picture tube 20. As a result of the above, the sub-screen B is reduced to 1/3 and displayed on the picture tube 20 in a predetermined area of the main screen as shown in FIG.

Next, the control circuit 19 will be explained.

The control circuit 19 includes a switching signal generation circuit 21, a comparison circuit 22, a down counter 23, a zero detection circuit 24, an AND gate 25, etc. as shown in the figure. A switch 26 is connected to the load terminal LD of the counter 23. This switch 26 is a switch for selecting whether or not to display a sub-screen. In this embodiment, when this switch 26 is OFF, sub-screen B is displayed;
When this switch 26 is turned on, the sub-screen B is gradually erased from the lower end upward.

A read address RA is added to the switching signal generation circuit 21 from the read address generation circuit 17,
Based on this, the switching signal Sc for inserting the sub-screen signal S into a predetermined area of the main-screen signal SM is formed.

When the switch 26 is OFF and a sub-screen is inserted, "64" is loaded into the counter 23, and the rHJ signal is applied from the zero detection circuit 24 to the enable terminal EN.

At this time, the counter 23 is in a load priority state, and its count value X is fixed at "64".

The comparison circuit 22 compares the read address RA and the count value X. When inserting a subscreen, the above RA changes from "0" to "63", so in this case, RA<
The relationship is x. At this time, the output rHJ of the comparator circuit 22 is the output rHJ of the AND gate 25.
added to.

Therefore, the switching signal Sc passes through the AND gate 25 as it is and controls the synthesis circuit 18.

This preserves the insertion of subscreens.

Next, when the switch 26 is turned on in this state, the counter 23 operates, and the main screen vertical synchronization signal ■ is applied to the clock terminal CL. Count down from "64".

In the comparison circuit 22, when RA≧X, the comparison output becomes “L” and the AND gate 25 is closed. Therefore, in the first field after the switch 26 is turned ON, x=63, whereas R
When A becomes 63, the scanning line corresponding to RA=63 of the sub-screen, that is, the scanning line of 64 main ports is first erased. In the next field, x=62, so 63 main scanning lines are erased. In this way, one scanning line is sequentially erased from the bottom for each field, and the entire sub-screen is erased in a time corresponding to 63 fields, that is, about 1 second. Then, when x-〇 is reached, the output of the zero detection circuit 24 becomes rL.
J and the enable is released.

According to the above, when the switch 26 is turned on, the sub-screen is erased from the bottom, so that a preferable feeling can be obtained. In the embodiment, the sub-screen is erased from the bottom, but it may be erased from the top. In that case, the counter is configured to count up the signal 4. Also, the horizontal synchronization signal H is output from the counter.

By counting , the sub-screen can be erased from the left or right.

Next, the write control circuit 27 that controls the write address generation circuit 12 will be explained.

As mentioned above, writing to the memory 10 is performed on one out of three scanning lines in synchronization with the signals Vs and Hs, and continuous writing is performed on signals 9 and H at three times the writing speed. done synchronously. In this case, since the main screen signal and the sub-screen signal are usually completely different signals, the signals ①A and HI and V5 and H3 are not synchronized. This causes the following problems.

For example, if a signal written in an odd field of the sub screen is read out in an even field of the main screen, the order of the scan lines of one frame screen when the sub screen is inserted into the main screen will be out of order, and the scan lines will be out of order. The hierarchy may be reversed. Further, the memory 10 performs reading while writing, but since the reading speed is faster than the writing speed, reading overtakes writing in the middle of one field. In that case, after overtaking, the data in the previous field will be read. That is, for example, if the above overtaking occurs in a field on the main screen,
In that field, even field signals and odd field signals are read out to form a sub screen in the same field of the main screen. Even in this case, the vertical relationship of the scanning lines may be reversed.

The write control circuit 27 is provided to solve the above problem, and is configured as shown in FIG.

In FIG. 2, the write control circuit 27 has signals Vs,
A field detection circuit 28 detects even fields and odd fields of the sub-screen based on Hs, and signals
, 4, an address comparison circuit 30 that compares the write address WA (!: read address RA), and each of the circuits 28, 29, . and an address control circuit 31 that controls the write address generation circuit 12 based on the output of the write address generation circuit 30.

According to the above configuration, a regular scanning line is selected depending on whether the field on the sub-screen and the field on the main screen are the same or different, and writing is performed at a ratio of 1 in 3 trees, and the correct scanning line is selected. Interlacing can be done. Further, the comparator circuit 30 can detect the point in time when the address RA overtakes the WA, and select a normal scanning line according to the field at that time.

〔Effect of the invention〕

When the switch for erasing the sub-screen is operated, the sub-screen is gradually erased from the edge, so that the lingering sound after erasing remains and a pleasant feeling can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an embodiment of the write control circuit of FIG. 1, and FIG.
The figure is a diagram showing the screen of a two-screen television receiver. In addition, in the symbols used in the drawings, SM'-'-----------------------------m=----------・・−Sub screen signal I L−−−−−・−・・−・−−−−−One synthesis circuit 19−・−−−−−−−−・−−−−Control circuit 2
1-・-・−・−−−−−−−m=−・Switching signal generation circuit 22・−−m=−−−・・・−・−・Comparison circuit 23−・～・・・−・−・・−・−・Counter.

Claims (1)

[Claims] In a two-screen television receiver in which a second screen is inserted into the first screen by a switching signal for switching between two video signals, the insertion area of the second screen is The two-screen display is characterized in that the second screen is gradually erased from the edge of the second screen by providing a means for creating a control signal that narrows the screen as the second screen progresses, and controlling the switching signal using the control signal. TV receiver.