JPS6199438A - Gpib transmission circuit system - Google Patents

Abstract

PURPOSE:To make the constitution of the whole of a transmission circuit small-sized considerably and transmit various information signals required for all data transmission and control by connecting two system control circuits by a signal line and controlling data transmission and electric apparatus between two electric apparatus through the signal line. CONSTITUTION:The first bus 13-1 for the system control circuit is connected to the first system control circuit 11 through a connector 12-1, and this bus 13-1 is connected to a bus 13-2 for the electric apparatus through a connector 12-2. The first electric apparatus and the first controller device are connected to this bus 13-2. Meanwhile, the second bus 17-1 for the system control circuit is connected to the second system control circuit 15 through a connector 16-1, and a connector 17-2 is connected to this bus 17-1. The second electric apparatus and the second controller device are connected to this bus 17-2.

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention relates to a transmission circuit system that remotely transmits data and controls the data between remotely located electrical devices via communication lines. It is.

"Prior Art" Various information signals are sometimes transmitted via communication lines in order to transmit data and control between a plurality of electrical appliances installed remotely. In such cases, in conventional devices, the signal from the status output pin of the control LSI of the transmission circuit is detected by the PU installed in the transmission circuit. The transmission between them was performed under CPUJ'lllliI] control.

The control performed by these CPUs is performed by software.
Dedicated LSI, CPU, ROM, RAM for transmission circuit
, a serial interface, etc. are necessary for the configuration, which increases the size of the entire transmission circuit, and its operation is also complicated.

"Problems to be Solved by the Invention" This invention aims to solve the problems of the conventional transmission circuit described above, such as the increase in the size of the device configuration and the complexity of the operation. It was downsized to C.
A GPIB transmission circuit system that does not use a PU and has a logic circuit configuration for the system control circuit in the transmission circuit, which enables all data transmission and transmission of various information signals necessary for control. This is what we offer.

"Structure of the Invention" The present invention includes a first electrical device and a first controller device connected to a first bus, a second electrical device and a second controller device connected to a second bus, A first bus is connected to the first system control circuit through a first bus receiver and a first bus driver, and a second bus is connected through a second bus receiver and a second bus driver. The first and second system control circuits are connected to a second system control circuit, and the first and second system control circuits are connected by a signal line, and data is transmitted between the first electric device and the second electric device through the signal line. This is applied to the GPIB transmission circuit system where control is performed.

In the present invention, the first system control circuit includes first and second functions that detect the occurrence of a data valid signal on the first or second bus side, respectively.

First and second OR circuits are provided for detecting the occurrence of a controller on the controller and the first or second bus side, respectively.

Further, the generally one system control circuit includes a first state variable logic array and a first output variable logic array. The corresponding input lines of the first state variable Rosock array include the output terminals of the first and second free, defro, and pull circuits, the output terminals of the first and second OR circuits, and the first bus ready for reception. The signal line and the output terminal of the first reset signal generation circuit are connected.

It holds state variable signals output from the first state variable logic array in response to the logical values of the signals on these input lines, inputs these state variable signals to the first state variable logic array, and A first holding circuit input to one output variable logic array is connected to the output end side of the first state variable logic array.

In addition, the corresponding input lines of the first output variable Ronok array include a state variable signal output line from the first state variable Ronok array, a controller generation signal line on the first bus side, and an output terminal of the first reset signal generation circuit. are connected to each other. The first output variable logic array outputs drive signals and handshake control signals for driving the first bus driver and bus receiver.

On the other hand, the second system control circuit includes first and second F-flops that detect the occurrence of a data valid signal on the second or first bus side, respectively, and a first or second F-flop on the first or second bus side. First and second OR circuits are provided that respectively detect the occurrence of the controller. Additionally, the second seven stem control circuit is provided with a second state variable logic array and a second output variable logic array.

The corresponding input line of the second state variable logic array has
The output terminals of the first and second flip-flops, the output terminals of the first and second OR circuits, the reception ready signal line of the second bus, and the output terminal of the second set signal generation circuit are connected. There is.

It holds state variable signals output from the second state variable logic array in response to the logical values of the signals on these input lines, inputs these state variable signals to the second state variable logic array, and A second holding circuit input to the output variable logic array is connected to the output end side of the second state variable logic array.

In addition, the corresponding input lines of the second output variable logic array include a state variable signal output line from the second state variable logic array, a controller generation signal line on the second bus side, and an output from the second reset signal generation circuit. The terminals are connected to each other. The second output variable logic array outputs drive signals and handshake control signals for driving the second bus driver and bus receiver.

"Embodiments" The GPIB transmission circuit system of the present invention will be described in detail below based on embodiments using the drawings.

This invention relates to the FiGPIB transmission circuit system,
A first electrical device and a first controller device are connected to a first bus, a second electrical device and a second controller device are connected to a second bus, and a first bus is connected to a first bus. A second bus is connected to a first system control circuit via a bus receiver and a first bus driver, while a second bus is connected to a second system control circuit via a second bus receiver and a second bus driver. connected, and the first and second system control circuits are connected by a signal line,
Information signals are transmitted between the first electrical device and the second electrical device through the signal line.

FIG. 1 is a block diagram showing the overall configuration of the GPIB transmission circuit system of the present invention. is connected to this first bus 13-1.
is the first bus 1 for electrical equipment via the connector 12-2.
3-2.

A first electrical device and a first controller device are each connected to this first bus 13-2.

In the embodiment, connectors 12-3 to 12-7 are connected to a first bus 13-2 for electrical equipment, and first electrical equipment 14-1 to 14-5 are connected to each other via these connectors.
is connected. In the embodiment, five electric devices are connected to the first bus via connectors, but at least one electric device (talker) with a data transmission function and one electric device with a data reception function are connected. It is necessary that there is an electrical device (listener) with a 7J for electrical device.
! , 1, the first controller device 10 is connected to the bus 13-2 of the buses 13-2. In the embodiment, this controller device 10 is built into a first electrical device 14-1.

On the other hand, the connector 16 for the second 7-stem control circuit 15
-1 via a second bus 17-1 for system control circuitry;
is connected, and this second bus 17-1 is connected to the connector 17-
2 is connected to a second bus 17-2&C for electrical equipment. A second electrical device and a second controller device are each connected to this second bus 17-2.

In the embodiment, connectors 17-3 to 17-7 are connected to a second bus 17-2 for electrical equipment, and second electrical equipment 18-1 to 18-5 are connected via these connectors, respectively.
is connected. Also, a second controller device 9 is connected to the second bus 17-2 for electrical equipment via a connector 17-8. In the embodiment, this second controller 9 is connected to the electrical equipment 2; 18-1. It is built-in.

The first and second system control circuits 11.15io'l are connected by signal lines 19 and 20. These signal lines are composed of, for example, optical fiber cables. Line 19 is for transmitting various information signals converted from the first system control circuit 11 to the second system control circuit 15. The signal line 20 is a signal line for transmitting various parallel/real-converted information signals from the second system control circuit 15 to the first system control circuit 11.

FIG. 2 is a diagram showing the details of the configuration of the first system control circuit 11, and the second system control circuit 1
5 parts also have exactly the same structure.

The first system control circuit includes first and second flip-flops that respectively detect occurrence of a data valid signal on the first or second bus side.

First and second OR circuits are provided to respectively detect the occurrence of a controller on the first or second bus side. Further, the first system control circuit is provided with a first state variable logic array and a first output variable logic array.

That is, the first system control circuit 11 has a system control PL.
A 21 is provided, and this system control PLA 21 is composed of a state variable circuit and an output variable circuit, which will be described later. The system control PLA 21 has terminals 22-1 to 22-1.
0 is set.

On the other hand, 23-1 to 23-5 are a data valid signal line (hereinafter abbreviated as DAV line) and an interface clear signal line (hereinafter abbreviated as IFC-, IJ) of the first bus.
, a command signal line (hereinafter referred to as the ATN line), an acceptance ready signal line (hereinafter referred to as the NRFD line), and an acceptance completion signal line (hereinafter referred to as the NDAC line). Also 23-
6 is a general line, and as described later, an interrupt signal (hereinafter SR
(abbreviated as Q signal), data end indication signal (hereinafter referred to as EOI)
χ remote local switching signal (hereinafter referred to as RE)
(abbreviated as N signal), data signals DIO1 to DIO8
Contains each line.

The DAV line 23-1 is a transmission line for a data valid signal (hereinafter abbreviated as DAV signal), and when there is no valid data signal on the first bus, the logical value of the signal is P1'', When a valid data signal is present on the first bus, the first
The logic value of the DAV line signal becomes 0'' due to the DAV signal emitted from the electrical equipment.The IFC line 23-2 is sent from the first controller to the first bus to clear the interface to initialize the interface. signal (hereinafter referred to as I
When an FC signal (abbreviated as FC signal) exists, the logic value of the signal changes from °'1" to '0".

The ATN line 23-3 is connected to the active controller (hereinafter referred to as A).
This is a transmission line for TN signals (abbreviated as TN signals), and when there is a data signal on the first bus, the logic level of the signal is "1", but the signal is transmitted from the first controller to the first bus. When the ATN signal is present, the logic value of the signal becomes 0''.

NRFD line 23 line 3 acceptance ready signal (hereinafter NRFD
(abbreviated as "signal"), and the first
When all of the electric devices are ready to receive various information signals, the resulting NRFD signal changes the logic value of the signal from '0' to '1'.

The NDAC line 23-5 is a transmission line for an acceptance completion signal (hereinafter abbreviated as NDAC signal), and the signal is transmitted by the NDAC signal that is issued when all the first electric devices on the first bus side have completed accepting information signals. The logical value changes from 0# to Pa1''.

In addition, the composite line 23-6 includes an SRQ line, which is a transmission line for an SRQ signal issued when an electrical device issues an interrupt request to a controller device, and an REN signal, which is used to switch between remote control and local control of the electrical device. The REN line which is a transmission line, the data input/output line DIOI to DI08 line, the data input/output line (DIO line) indicates the end when the data is a multiple byte string, and together with the ATN line and the parallel hole. EOI lines, which are transmission lines for EOI signals indicating that execution is in progress, are connected in parallel.

In the following description, this invention will mainly be explained by referring to the first
The explanation will focus on the system control circuit. The second system control circuit on the second bus side also includes a circuit having exactly the same configuration as the first system control circuit.

The DAV line 23-1 has the first Nogsdraino (24-1
The output terminal of the first bass reflex amplifier 25-1 is connected to the input terminal of the first bass reflex amplifier 25-1. The input terminal of the bus driver <24-1 is connected to the set terminal t of the flip-flop f26, and the output terminal t(Q) of the flip-flop 26 is connected to the terminal 22-1 of the system control PLA 21.

The output terminal of the bus receiver 25-1 is the free lag flop 2.
It is connected to the set terminal t of 7, and the flip-flop f27
The output terminal t(Q) is the terminal 2 of the system control PLA21.
Connected to 2-2n. Also flip flop f26 and 2
The reset terminal tR of 7 is connected to the terminal 22-3 of the system control PLA 21.

IFC line 23-2 has the first nox line 24-2.
The output terminal of and the input terminal of the first 9 thread J25-2 are connected. The input terminal of the bus try <24-2 is connected to one input terminal of the OR circuit 29, and the output terminal of the OR circuit 29 is connected to the terminal 22-4.

Further, the output terminal of the bus receiver 25-2 is connected to one input terminal of the OR circuit 30, and the output terminal of this OR circuit 30 is connected to the terminal 22-5.

The ATN line 23-3 is connected to the output terminal of the first bus driver 24-3 and the input terminal of the first bus driver 25-3. The input terminal of the bus driver 24-3 is connected to another input terminal of the OR circuit 29. On the other hand, the output terminal of the bus reflector 25-3 is connected to the other input terminal of the OR circuit 30. Further, ATN line 23-3 is connected to terminal 22-6 of system control PLA 21.

NRFD line 23 is connected to the output terminal of the first bus driver 24-4 and the input terminal of the first bus receiver 25-4. NRFD line 23 lines 3-prong system control PLA
Connect to terminal 22-8 of 21.

The NDAC line 23-5 is connected to the output terminal of the first bus driver 24-5 and the input terminal of the first bus receiver 25-5. The output terminal of the AND circuit 31 is connected to the input terminal of the bus driver 24-5, and the terminal 22-7 is connected to one input terminal of the AND circuit 31. The other input terminal of the AND circuit 31 is configured to receive a bus driver input of the ND AC line in the first system control circuit 11).

The output terminal of the first bus driver 24-6 and the input terminal of the first bus receiver 25-6 are connected to the composite line 23-6. Further, the output terminal of the first reset signal generation circuit 33 is connected to the terminal 2.2-10.

Furthermore, the terminal 22-9 is connected to the first bus driver 24-1 to 24-2.
4-6 and the control terminals of the first bus receivers 25-1 to 25-6, respectively, and a control signal for controlling the operation of each bus driver and bus receiver is issued from the terminal 22-9.

The configuration of the bus driver and bus receiver connected to each line in FIG. 2 is as follows: first bus driver 24-1 connected to DAV line 23-1,
FIG. 3 shows the detailed configuration of the P-25-1 as an example.

FIG. 4 shows in detail the structure of the first bus driver and first bus receiver connected to the composite line 23-6 of FIG. 2.

That is, the input terminal of the first bus driver 24-6 is NAN
Each of the D circuits 35-1 to 35-11 is connected to one input terminal, and the other input terminal of these NAND circuits is connected to the terminal 22-9. On the other hand, each NAN
The input terminals of the inverting circuits 36-1 to 36-11 are connected to the output terminals of the D circuit, respectively, and the output terminals of these inverting circuits are connected to the output terminals of the first bass register 7-pa 25-6 in FIG. It is said that Further, the set terminals of each of the inversion circuits 36-1 to 36-11 are connected to the input terminal of the first bus driver 24-6.

The output terminals of the NAND circuits 35-1 to 35-3 are connected to an SRQ line 23-6-1, an EOI line 23-6-2, and an EOI line 23-6-2, respectively.
REN line 23-6-3 is connected. Also, NAND circuit 3
Output terminals 5-4 to 35-11 have D10 lines 23-6-4 to 23-6-1, which are human output lines for data, respectively.
1 is connected.

In the initial state, all bus receivers are activated by a control signal supplied from terminal 22-9, and the bus receivers are set to the transmitting state.

The 7-stem control PLA 21 in FIG. 2 has a circuit configuration as shown in No. 5J, and the state variable Ronok array 41 and the first output variable logic array 42 shown in the figure.
have logic circuit configurations as shown in FIGS. 6 and 7, respectively. The input lines of the first state variable logic array 41 are connected to the first and second seven litho,
The output terminals of the first and second logic circuits 30 and 29 are connected to the NRFD line 23-4 and the output terminal of the first reset signal generation circuit 33, respectively.

In the first state, a holding circuit 41-R constituted by, for example, a flip-flop is connected to the output end side of the multi-state variable Rosok array 41, and this holding circuit 41 holds the output signal of the first state variable Rosok array 41. , these output signals are input to a first state variable logic array 41, and these output signals are input to a first output variable logic array 42. The first output variable Ronok array 42 is the seventh
The logic circuit has the configuration shown in the figure, and the output terminal of the first state variable array 41, the ATN line 22-6, the output terminal of the R7 signal generation circuit 33 are connected to the corresponding input terminals. From the first output variable logic array 42,
Drive signals C0NTl to C0NT4 that drive the respective bus drivers and bus receivers via terminals 22-9.
is output. Further, the first output sock array 42 outputs a handshake control signal.

The first system control circuit 11 detects on which side of the first and second buses the talker is present based on the output signals of the first and second seven busses 27;
and the output signal of the second OR circuit 30°29
and detecting which side of the second bus the controller is present.

Based on this detection result, a corresponding drive signal is emitted from the first output variable Ronok array 42 of the first 7-stem control circuit 11, and this drive signal causes each of the first bus side The bus drivers and bus registers are selectively driven.

The transmission direction of the various information signals is selected by this selection drive, and the various information signals are quickly and reliably transmitted without transmission errors by the band/aff control signal outputted by the multi-ronok array 42 as the first output.

The talker detection operation on the first 7-stem control circuit 11 side will be explained.

For example, when it is confirmed that a data signal is to be transmitted from the first electrical device 14-1 to a predetermined second electrical device, the first electrical device 14-1
A data signal from -1 is provided to the first bus. 1st
When a valid data signal is sent to the first bus,
The electric machine ie:i14-1 emits a DAV signal, and the DAV
The logic value of the signal on line 23-1 becomes 0''.

Since the bus receiver 25-1 is initially set to the transmitting state, this DAV signal is supplied to the flip-flop 27 of the first system control circuit 11, and the DAV signal is supplied to the terminal 22-2 of the first system control circuit 11. The logic value of the signal at the output terminal 22-2 of the flip-flop 27 becomes "0".
0'' and the logical value of the signal at the terminal 22-6 is 1'', thereby detecting the presence of a talker on the bus side of a1.

Figure 8 (
4), signals appear at the terminals 22-4, 22-5, 22, in this case the row shown in FIG. The AND circuit 45-4 obtains the AND signal with the signal Q4 applied to the numerical logic array 41, and this signal is applied to the OR circuit 46-5.

is held in the holding circuit 41-R.

Thus, in this case, the signal Q held by the holding circuit 41-R is applied to the first output variable logic array 42. At this time, the logical value of the signal at the terminal 22-6 supplied to the output variable logic array 42 is 1'' as shown in FIG. 9(3), and at this time the R3TC signal supplied to the terminal 48 is
The logical value of the 4 signal is PA1'', and the logical value of the RST signal applied to the terminal 22-10 is PA0''. The R8TCt signal applied to terminal 48 is used to adjust the operation of the output variable Ronok array. In this state, Figure 7 (3
), and as shown in FIG. 9(3), the drive signal C0NT1. C0NT6. C
0NT4 is output.

These drive signals drive the NRF'D line 23-4°ND.
The bus drivers 24-4 and 24-5 become active and the AC line 23-5 is set to a receiving state. Also, the bus receiver 25-1 is activated, the DAV line 23-1 is set to the transmitting state, and the general line 23-6 is activated to the bus receiver 25.
-1. The inverting circuits 36-4 to 36-11 and 36-2 are set to the active state: As a result, the DIO line and the E lead line are set to the transmitting state.

ATN line 23-3, IFC line 23-2, REN line 23-
Regarding control lines such as 6-3 and SRQ line 23-6-1, the first
Alternatively, the direction is set based on information on which side of the second bus the controller is located.

The operation of the first system control circuit when a talker occurs on the second bus side will be explained.

The DAV signal from the output terminal of the bus register < 25-1 of the second system control circuit is transmitted to the first mass-side bus driver 24-1 via the second and first 7-stem control circuits.
is applied to the input terminal of Therefore, the logical value of the signal at the output terminal 22-1 of the second flip-flop 26 of the first system control circuit becomes '0''. In this state, if the logical value of the signal at the terminal 24 is It l II, then The presence of a talker on the other side (second bus side) is stored in the first system control circuit.

When the presence of the talker on the other side (second bus side) is memorized, the first system control circuit sends an NRFD signal indicating that all of the first electrical devices are ready to accept data, and after receiving the data. It is necessary to send an NDAC signal indicating that the first electrical device has completed receiving data to the second 7-stem control circuit. NRFD line terminal 23-4 on the first bus side
After confirming that the logical value of the signal becomes "1" and that all electrical devices on the first bus side are ready to accept data, the first system control circuit switches each line.

As shown in FIG. 8 (5), the human power of the deaf variable Ronok array is such that the logic value of the signals at terminals 22-1 and 22-10 is "0".
'', terminals 22-2.22-4.22-5.

The logical value of the signal 22-8 is °'1''. In this state, a signal appears in the row shown in (5) in FIG. -5, and the state variable Ronok array 41 outputs a signal Q4, which is held in the holding circuit 41-R.The state variable Ronok array 41 inputs the signal Q4 to the output variable logic array 42.

This state corresponds to FIG. 9 (4), and a signal appears in the output variable array 42 in the row shown in FIG. 7 (4).
C0NT, , C as the output of the AND circuit 45-10
0NT3°C0NT4 and NDACC signals are generated. These signals cause the bus driver 24-1 of the DAV line 23-1 to become active and enter the receiving state. D.I.
O line and EOI line are general line 23-6ONAND circuit 35
-2 and 35-4 to 35-11 are set to active to enter the receiving state; NRFD line 23-4 and NDAC line 23-5 are set to active by bus receivers 25-4 and 25-5, respectively. The device enters the transmitting state.

In this way, in this invention, when it is confirmed that a talker exists on either the first bus side or the second bus side, the 7-stem control circuit detects this and connects the DAV line, which is a data signal line, to the DAV line, which is a data signal line. DIO line - EOI line and AT which is the control line
The signal flow direction of the N line, IFC line, REN line, and SRQ line is controlled by driving the respective bus drivers 9 and bus receivers, and various information signals are quickly transmitted based on the bandon-ake operation.

The information regarding the talker stored in the flip 20 tabs 26 and 27 is erased by applying a reset signal to the terminal 22-3 through the terminal 22-6 when the logic value of the signal on the ATN line becomes 0.

In this case, talker detection is not performed until the next logical value of the signal on the ATN line becomes "°]".

Every time the talker moves between the first bus side and the second bus side, the logic value of the signal at the output terminal of the flip 70 27 or 26 becomes '0'. The direction of the talker is determined.

FIG. 10 is a flowchart showing the detailed control operation of talker detection described above, and the reference numerals used in the figure are the same as those used in FIG. 2.

　　　　.

The operation when detecting the presence of a controller on the first bus side will be described.

As already mentioned, in the initial state, the bus registers on the first bus side -'25-1 to 25-6&-! .

All are set to active and ready for transmission.

For this reason, the information on the first bus side is sent to the first system control circuit.@ When a controller is established on the first bus side, the information from the ATN line 23-3 or the IFC line is sent by a signal issued from the control device. The logical value of the signal 23-2 becomes 0.

Therefore, the logical value of the signal at the terminal 22-5 connected to the output terminal of the OR circuit 30 becomes 0'', and the system control circuit 11 stores information indicating that there is a controller on the first bus side. .

1 after the logic value of the signal at terminal 22-6 becomes “°0”.
Within 7 Sn5ec, the logic value of the signal on the terminal 22-7 is set to "o", the logic value of the signal on the NDAC line 23-5 is set to "0", and this state is maintained for 250 μsec. This is a waiting time operation using the NDAC line, which is determined to quickly process the acceptance on the second bus side within the system control circuit 11 on the first bus side.

This state is shown in FIG. 8 (2), in which the terminals 22-5° 22-10 of the quaray 41 are
The logical value of the signal at terminal 22-4 is 0'', and the logical value of the signal at terminal 22-4 is 0'1''. This corresponds to the appearance of a signal in the row shown in FIG. 6 (2) in the first state variable logic array 41, and the signal Q1 is held in the holding circuit 41-R by the output of the AND circuit 45-2. Be it. This signal Q is input to the first state variable logic array 41 and is also input to the first output variable logic array 42 as shown in (5) of FIG. Terminal 22-6 to which the input of logic array 41 is connected
．． The logic value of the signal 22-10 is °゛0'', and the variable signal Q
Only 1 is entered. This is shown in Figure 7 (5)
Indicates that a signal appears on the line indicated by .

From the first output variable Ronok array 42, the AND circuit 4
5-11 via C0NT,', C0NT3. N
RFDS signal and DAVFFC signal are output.

These drive signals issued from the terminal 22-9 cause the E01 line 23-6-2, the TFC line 23-2, the ATN line 23-3, the REN line 23-6-3, the DAV line 23-1,
D10a 23-6-4 to 23-6-11 are each set to the transmission size by actively setting the Renova lever.

On the other hand, NRFD line 23-4, NDAC line 23-5, SRQ
Lines 23-6-1 are set to the receive state as their respective bus drivers are set active.

Even if the logic value of the signal on the ATN line 23-3 returns to 1'', the first
The information that the controller was present on the bus side is stored in the first system control circuit 21. When a reset signal is applied from the reset circuit 33 to the terminal 22-10, the information that the controller of the first system control circuit 21 exists is erased.

The operation when detecting the presence of a controller on the second bus side will be described.

When a controller is generated on the second bus side and the logic value of the signal on the IFC line or ATN line becomes 0'', this signal is transmitted via the second system control circuit 15, first system control circuit 11. The logical value of the signal at the input terminal of the bus driver 24-2 or 24-3 becomes 0". Therefore, the logical sum circuit 27
The logic value of the signal at the terminal 22-4 connected to the output of the bus becomes PaO'', and this is stored in the 7-stem control circuit 21 as information that the controller is present on the second bus side.

Each bus driver and bus receiver is switched by the drive signal at the terminal 22-9 so that the controller is on the second bus side. This state is shown in Figure 8.
The state variable Ronok array 4 is shown in (3).
The logic value of the signals at the input terminals 22-4 and 22-10 of 1 is "0", and the logic value of the signal at the terminal 22-5 is 1". In this state, the 6th input terminal of the state variable Ronok array 41
A signal is generated in the row indicated by (3) in the figure, and the AND circuit 45-
3, the signal Q2 is held in the holding circuit 41-R via the OR circuit 46-3. This signal Q2 is input to the first state variable Ronok array 41, and the first
output variable logic array 42. Therefore, the first output variable Ronok array 42 generates a signal in the row shown in (6) of FIG. 7, and the C0NT, C0NTa, and DAVFFC signals are obtained from the respective OR circuits via the AND circuit 45-12.

These drive signals cause the NRFD line 23-4, NDA
C lines 23-5 are set to a transmit state by having their respective bus receivers set active.

EOI line 23-6-2, IFC line 23-2, ATN line 2
3-3REN line 23-6-3, DAY line 23-1, DI
O lines 23-6-.1 to 23-6-11 are set to a receiving state by setting their respective bus drivers to active.

Even if the logic value of the signal on the ATN line 23-3 returns to °l, the information that there is a controller on the second bus side is stored in the first system control circuit 21.Reset circuit 33 When a reset signal is applied to terminal 22-10 from , the information that the controller was present on the second bus side is erased.

FIG. 11 is a flowchart showing the controller detection operation described above. The symbols in the figure are the same as those used in FIG. 2.

The switching control of the transmission direction of the transmission line of various information signals performed by talker detection and controller detection as described above on the first system control circuit side is performed in exactly the same way on the second system control circuit side.

``Effects of the Invention'' In the present invention, a 7-stem control circuit is provided with a state variable logic array and an output variable logic array composed of logic circuits. In addition, the 7-stem control circuit is provided with a flip-flop and an OR circuit, and this OR circuit determines whether the controller is generated on the first or second side. It is detected on which side of the first and second buses the talker has occurred, and it is determined on which side the talker is currently present.

Based on these detection judgment outputs, the state variable ronok array and the output variable ronok array generate corresponding drive signals, and these drive signals set the respective bus drivers or bass levers to the active state. The flow directions of various information signals between the first and second system control circuits are set.

Therefore, the entire structure is miniaturized and configured with a simple circuit without requiring a CPU, and software control is not required, and a reliable handshake operation is performed between the first and second electric devices. Even if there is a difference in the processing time of the listeners, all the listeners can transmit various information signals in accordance with the speed of the slower listener. The information signals transmitted in this way allow for quick and accurate data transmission and control of electrical equipment without being affected by signal propagation delays caused by serial-to-parallel conversion, and with reliable handshake operations, data loss and erroneous data can be avoided. This can be done without any occurrence of Furthermore, the GPIB transmission circuit system of the present invention makes it possible to extend the group length per device from 2 m in the conventional GPIB transmission circuit system to 2 km.

As explained in detail above, according to the present invention, the entire circuit configuration is significantly miniaturized without requiring CPLI in the circuit configuration, and the electrical equipment can be quickly and accurately remotely installed with handshake operation. It becomes possible to provide a GPIB transmission circuit system capable of transmitting data between devices and controlling devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of the GPIB transmission circuit system of the present invention, FIG. 2 is a block diagram showing the configuration of the main part of an embodiment of the GPIB transmission circuit system of the invention, and FIG. 3 is the block diagram of the present invention. A fourth circuit diagram showing the configuration of a bus driver and a bus receiver in an embodiment of the GPIB transmission circuit system of
The figure is a block diagram showing the detailed configuration of the main parts including the data transmission line in the embodiment of the GPIB transmission circuit system of the present invention, and FIG. 5 is the system control in the embodiment of the GPIB transmission circuit system of the present invention. A block diagram showing the configuration of the state variable Ronok array and output variable logic array portion of the circuit, FIG. 6 is a circuit diagram showing the configuration of the state variable Ronok array in an embodiment of the present invention, and FIG. 7 is a block diagram showing the configuration of the state variable Ronok array in the embodiment of the invention. FIG. 8 is a diagram showing the input/output signals of the state variable Ronok array in the embodiment of the present invention; FIG. 9 is a diagram showing the input/output signals of the output variable Ronok array in the embodiment of the present invention. , FIG. 10 is a flowchart showing the control state of talker detection in this invention, and FIG. 11 is a flowchart showing the control state of controller detection in this invention. 9: second controller device, 10: first controller device, 11: first system control circuit, 13-1.1
3-2: First bus, 14-1 to 14-5-first electrical equipment, 15: Second system control circuit, 17-1.17
-2: Second bus, 18-1 to 18-5: Second electrical equipment, 19, 20: Signal line, 22-1 to 22-10: Terminal, 24-1, 24-2...: Bus driver, 25-1
．． 25-2...: Bass play: / =Z, 26, 27
:Flip-flop, 29.30: OR circuit, 33:
Reset signal generation circuit, 41: state variable rossock array, 42: output variable rossock array.

Claims (1)

[Claims] (1) A first electrical device and a first controller device are connected to a first bus, a second electrical device and a second controller device are connected to a second bus, and the first bus is a first bus receiver and a first bus driver;
system control circuit, and the second bus is connected to a second system control circuit.
is connected to a second system control circuit via a bus receiver and a second bus driver, the first and second system control circuits are connected by a signal line, and the first electric device is connected to the second system control circuit through the signal line. In the GPIB transmission circuit system in which information signals are transmitted between the electronic device and the second electric device, the first system control circuit is provided with a signal indicating that a data valid signal has been generated on the first or second bus side. First and second flip-flops for detecting and first and second OR circuits for detecting the occurrence of a controller on the first or second bus side are provided, and the first system control circuit is provided with a first state variable logic array and a first output variable logic array;
Corresponding input lines of this first state variable logic array include output terminals of the first and second flip-flops, output terminals of the first and second OR circuits, and preparation for receiving the first bus. A completion signal line and an output terminal of the first reset signal generation circuit are connected to each other, and a state variable signal output from the first state variable logic array is held in accordance with the logical value of the signal on these input lines. , a first holding circuit that inputs these state variable signals to the first state variable logic array and inputs the first output variable logic array to the output end side of the first state variable logic array. and the corresponding input lines of the first output variable logic array include the state variable signal output line from the first state variable logic array, the controller generation signal line on the first bus side, and the first The output terminals of the reset signal generation circuits are connected to each other, and the first output variable logic array is configured to output a drive signal and a handshake control signal for driving the first bus driver and bus receiver. , the second system control circuit includes first and second flip-flops that detect the occurrence of a data valid signal on the second or first bus side, respectively; and on the second or first bus side. First and second logic circuits are provided for respectively detecting the occurrence of a controller, and the second system control circuit includes a second state variable logic array and a second output variable logic array; Corresponding input lines of the two state variable logic arrays are connected to the first and second state variable logic arrays.
The output terminal of the flip-flop, the output terminal of the first and second OR circuits, the reception ready signal line of the second bus, and the output terminal of the second reset signal generation circuit are connected, respectively. The state variable signals outputted from the second state variable logic array in correspondence with the logical values of the signals on the input lines are held, and these state variable signals are transmitted to the second state variable logic array.
A second holding circuit is connected to an output end of the second state variable logic array, and a second holding circuit is connected to the output end of the second state variable logic array.
The corresponding input lines of the second output variable logic array include the state variable signal output line from the second state variable logic array, the controller generation signal line on the second bus side, and the second reset signal. The output terminal of the generation circuit and the output terminal of the second reset signal generation circuit are connected to each other, and the second output variable logic array receives a drive signal and handshake control for driving the second bus driver and bus receiver. A GPIB transmission circuit system characterized by being configured to output a signal.