JPS6199337A - Etching method of semiconductor crystal - Google Patents
Etching method of semiconductor crystalInfo
- Publication number
- JPS6199337A JPS6199337A JP22150284A JP22150284A JPS6199337A JP S6199337 A JPS6199337 A JP S6199337A JP 22150284 A JP22150284 A JP 22150284A JP 22150284 A JP22150284 A JP 22150284A JP S6199337 A JPS6199337 A JP S6199337A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- mirror
- rie
- wafer
- plane
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005530 etching Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000013078 crystal Substances 0.000 title claims description 22
- 238000000034 method Methods 0.000 title claims description 17
- 238000001039 wet etching Methods 0.000 claims abstract description 13
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000007789 gas Substances 0.000 claims abstract description 7
- 238000001020 plasma etching Methods 0.000 claims abstract description 7
- 150000001875 compounds Chemical class 0.000 claims abstract description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 5
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims abstract description 4
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 claims abstract description 4
- 235000019404 dichlorodifluoromethane Nutrition 0.000 claims abstract description 4
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 claims description 2
- 239000012495 reaction gas Substances 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 7
- 238000005498 polishing Methods 0.000 abstract description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 abstract description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 6
- 230000007547 defect Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical group [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- -1 silicon ions Chemical class 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はｍ−ｖ族化合物半導体、例えばガリウム砒素（
ＧａＡｓ）等の（１１１）Ａ面を鏡面エツチングする方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to m-v group compound semiconductors, such as gallium arsenide (
This invention relates to a method for mirror etching the (111)A plane of materials such as GaAs).
ここで、（１１１）Ａ面は■族原子が表面に現れる側の
面を云い、（１１１）８面はその裏側の面に当たり、Ｖ
族原子が表面に現れる。Here, the (111) A plane is the side on which the group II atoms appear on the surface, the (111) 8 plane is the plane on the back side, and the V
Group atoms appear on the surface.
ｍ−ｖ族化合物半導体は珪素（Ｓｔ）に比しキャリアの
易動度が大きいこと、および禁制帯幅が大きいこと等の
利点を利用して高速で紫外線等の外来ノイズに強い大規
模集積回路−（ＬＳＩ）や、光通信用素子として実用化
されるようになった半導体材料である。Compared to silicon (St), m-v group compound semiconductors have advantages such as higher carrier mobility and larger forbidden band width, and can be used for large-scale integrated circuits that are high-speed and resistant to external noise such as ultraviolet rays. - (LSI) and semiconductor materials that have come into practical use as optical communication devices.
この材料の製造方法として、ボート成長法、引き上げ法
、エピタキシャル成長法等があるが、ＬＳＩ用としては
引き上げ法が最も多く採用されている。Methods for manufacturing this material include a boat growth method, a pulling method, and an epitaxial growth method, but the pulling method is most commonly used for LSI applications.
現在引き上げ法では多くの場合、結晶加工のし易さ、お
よび円形結晶の必要性（ＬＳＩの製造装置、例えばアラ
イナの治具等は円形ウェハを扱うようにできている）等
の理由から＜１００＞方向に引き上げて、この方向に垂
直にスライスして（１００）面の円形ウェハが得られる
。Currently, in most cases, the pulling method uses crystals with crystals of > direction and sliced perpendicular to this direction to obtain a (100)-plane circular wafer.
このようにして得られた（１００）面は結晶欠陥数が１
０４〜１０’ ｃｍ−”と多く、半導体素子特性の結晶
面内でのバラツキを大きくしている要因となっている。The (100) plane obtained in this way has a crystal defect number of 1.
04 to 10'cm-'', and is a factor that increases the variation in semiconductor device characteristics within the crystal plane.
従って現在ではこの結晶欠陥数を減らすために（１００
）面を得る引き上げ法のいろいろの改善が行われている
。Therefore, in order to reduce the number of crystal defects (100
) Various improvements have been made to the pulling method for obtaining surfaces.
さらに結晶欠陥数を減らす方法の１つとして、＜１１１
＞方向に結晶の引き上げを行うと、結晶欠陥数を約１桁
下げ得ることは既に知られているが、（１１１）Ａ面は
鏡面エツチングが困難のために実用化されていない、ま
た（１１１）８面はＡｓ等蒸気圧の高いＶ族の原子が表
面に現れるため、これらの原子が結晶から抜は出し易く
なり、従って結晶組成が不安定となりこの面を素子形成
に使用することは好ましくない。Furthermore, one method to reduce the number of crystal defects is <111
It is already known that the number of crystal defects can be reduced by about one order of magnitude by pulling the crystal in the > direction, but the (111) A plane has not been put to practical use because mirror etching is difficult, and ) Since V group atoms with high vapor pressure, such as As, appear on the surface, these atoms are easily extracted from the crystal, and the crystal composition is therefore unstable, making it preferable to use this surface for device formation. do not have.
上記のように＜１１１＞方向に結晶を引き上げて、１
結晶欠陥数を減らし、（１１１）Ａ面を半導
体素子製造に使用できるようにするために、（１１１）
Ａ面の鏡面エツチングを実現することが望まれる。As above, pull the crystal in the <111> direction and
In order to reduce the number of crystal defects and make the (111) A plane usable for semiconductor device manufacturing, (111)
It is desirable to achieve mirror etching of the A side.
引き上げ結晶は、通常５００μｍ程度の厚さにスライス
され、その後ケミカルおよびメカニカルに鏡面研磨され
たウェハ状態で入手される。このウェハを使って半導体
素子を製造する場合、鏡面研磨により結晶内に入ったダ
メージを取り除くために数μｍ程度の鏡面エツチングを
硫酸（ＨｚＳＯ＊）と過酸化水素水（Ｈ２０□）と水（
ｎ２ｏ）の混液を用いたウェットエツチングを行う。The pulled crystal is usually obtained in the form of a wafer that is sliced to a thickness of about 500 μm and then chemically and mechanically mirror-polished. When manufacturing semiconductor devices using this wafer, mirror etching of several micrometers is performed using sulfuric acid (HzSO*), hydrogen peroxide (H20□), and water (
Wet etching is performed using a mixed solution of n2o).
従来例によるウェットエツチングでは、（１００）面の
鏡面エツチングは可能であるが、（１１１）Ａ面の場合
は０．５μｍもエツチングしないうちに、多数のエッチ
ピットが発生し、ウェハ表面は凸凹になり、素子製造に
は使用できない状態となる。In conventional wet etching, it is possible to mirror-etch the (100) plane, but in the case of the (111) A plane, many etch pits occur before even 0.5 μm is etched, and the wafer surface becomes uneven. Therefore, it becomes unusable for device manufacturing.
上記問題点の解決は、ｍ−ｖ族化合物半導体の（１１１
）Ａ面を、最初反応性ガスを用いてリアクティブイオン
エツチングし、ついでウェットエツチングすることによ
り鏡面エツチングを行う本発明による半導体結晶のエツ
チング方法により達成される。The solution to the above problem is the (111
) This is achieved by the method of etching a semiconductor crystal according to the present invention, which performs mirror etching by first reactive ion etching the A side using a reactive gas and then wet etching.
なお、前記反応ガスとして二塩化二弗化炭素を用い、前
記ウェットエツチングにアンモニア水と過酸化水素水と
水との混液を用いると一層効果がある。Further, it is more effective to use carbon dichloride difluoride as the reaction gas and to use a mixed solution of aqueous ammonia, hydrogen peroxide, and water in the wet etching.
本発明者は鏡面エツチング方法として、反応性ガスを用
いたりアクティブイオンエツチング（ＲＩＥ）により研
磨ダメージを除去し、かつ鏡面を保ち、さらにＲＩＥに
よるダメージをウェットエツチングにより除去すること
により、欠陥数が少なく、表面準位も少ない完全に近い
状態の結晶表面が得られることを見出した。The present inventor has developed a mirror etching method that uses a reactive gas or active ion etching (RIE) to remove polishing damage, maintains a mirror surface, and further removes RIE damage using wet etching to reduce the number of defects. We found that a nearly perfect crystal surface with few surface states could be obtained.
第１図（ａ）、 （ｂ）は本発明の一実施例を示す結晶
の断面図である。FIGS. 1(a) and 1(b) are cross-sectional views of a crystal showing one embodiment of the present invention.
第１図（ａ）において、（１１１）Ａ面ＧａＡｓ基板（
ウェハ）１を、反応性ガスとして二塩化二弗化炭素（Ｃ
Ｃ１８Ｆ２）を用いてＲＩＢ法により５μｍ程度エツチ
ングする。In FIG. 1(a), a (111) A-plane GaAs substrate (
wafer) 1 and carbon dichloride difluoride (C
Etching is performed by about 5 μm using RIB method using C18F2).
ＲＩＥの条件は真空度は５Ｐａで、パワーは５０〜１０
０−である。The RIE conditions are a vacuum of 5 Pa and a power of 50 to 10
It is 0-.
このエツチングにより研磨ダメージは除去され、かつウ
ェハは鏡面状態を保っている。しかしこのままでは、Ｒ
ＩＥによるダメージがウェハ表面から中に数１００人存
在するので、つぎのウェットエツチングを行う。This etching removes polishing damage and keeps the wafer mirror-like. However, as it is, R
Since there are several hundred damage caused by IE on the wafer surface and inside, the next wet etching is performed.
第１図中）において、
アンモニア水（Ｎ１１．０■）：過酸化水素水（Ｈ２０
□）：水（１１，０）
＝３ｏ： １ ：ｔｓ （容量比）。In Figure 1), ammonia water (N11.0■): hydrogen peroxide water (H20
□): Water (11,0) = 3o: 1:ts (capacity ratio).
のエッチャントを用いて、約２０００人のウェットエツ
チングを行い、ＲＩＢによるダメージを除去し、ウェハ
を鏡面にする。Approximately 2,000 people wet-etched the wafer using an etchant to remove the RIB damage and make the wafer a mirror surface.
このようにして、ＲＩＥとウェットエツチングの組み合
わせにより、鏡面研磨のダメージが除去でき、かつウェ
ハ表面は鏡面の良好なエツチングができる。In this way, by combining RIE and wet etching, damage caused by mirror polishing can be removed and the wafer surface can be etched to a good mirror finish.
つぎに本発明により鏡面エツチングしたＧａＡｓウェハ
を用いた、電界効果トランジスタＣＦＥＴ）を示す。Next, a field effect transistor (CFET) using a GaAs wafer mirror-etched according to the present invention will be shown.
第２図は本発明による基板を用いたＧａＡｓ −Ｆ Ｅ
Ｔの断面図である。Figure 2 shows GaAs-FE using the substrate according to the present invention.
It is a sectional view of T.
図において、１は（１１１）Ａ面ＧａＡｓ基板で、２は
チャネル領域、３．４はソース、ドレイン領域、５はタ
ングステンシリサイド（ＷＳｉ）よりなるゲート電極、
６，７は金ゲルマニウム／金（ＡｕＧｅ／八Ｕ）をへ次
蒸着して形成したソース、ドレイン電極、８は二酸化珪
素（Ｓｉ（ｈ）よりなる絶縁層である。In the figure, 1 is a (111) A-plane GaAs substrate, 2 is a channel region, 3.4 is a source and drain region, 5 is a gate electrode made of tungsten silicide (WSi),
Reference numerals 6 and 7 are source and drain electrodes formed by successive vapor deposition of gold germanium/gold (AuGe/8U), and 8 is an insulating layer made of silicon dioxide (Si(h)).
チャネル領域２、およびソース、ドレイン領域３．４は
珪素イオン（Ｓｉ”）を注入して形成する。The channel region 2 and the source and drain regions 3.4 are formed by implanting silicon ions (Si'').
以上のようにして（１１１）Ａ面ＧａＡｓ基板に対して
も、通常の工程を用いて特性のすぐれたＦＥＴが得られ
た。As described above, an FET with excellent characteristics was obtained using a normal process using a (111) A-plane GaAs substrate.
実施例では、反応性ガスとしてＣＣ１ｚｈを使用したが
、他の反応性ガスを使用しても発明の要旨は変わらな゛
い。In the examples, CC1zh was used as the reactive gas, but the gist of the invention does not change even if other reactive gases are used.
またウェットエツチングも他のエッチャントを使用して
も、エツチング量が５０００人程度以下であれば、本発
明の効果は損なわれない。Further, even if wet etching or other etchants are used, the effects of the present invention will not be impaired as long as the amount of etching is about 5,000 or less.
以上詳細に説明したように本発明によれば、■−■族化
合物半導体の（１１１）Ａ面に対して鏡面エツチングは
可能となり、半導体素子製造に使用できるようになる。As described above in detail, according to the present invention, it becomes possible to perform mirror etching on the (111)A plane of a ■-■ group compound semiconductor, and it becomes possible to use it for manufacturing semiconductor devices.
第１図（Ｉｌ） 、 （ｂ）は本発明の一実施例を示す
結晶の断面図、
第２図は本発明による基板を用いたＧａＡｓ −Ｆ Ｅ
Ｔの断面図である。
図において、
１は（１１１）Ａ＠ＧａＡｓ基板、 ２はチャネル領域
、３．４はソース、ドレイン領域、
５はゲート電極、
６．７はソース、ドレイン電極、
８は絶縁層
を示す。FIGS. 1(Il) and (b) are cross-sectional views of a crystal showing one embodiment of the present invention, and FIG. 2 is a cross-sectional view of a crystal of GaAs-FE using a substrate according to the present invention.
It is a sectional view of T. In the figure, 1 is a (111)A@GaAs substrate, 2 is a channel region, 3.4 is a source and drain region, 5 is a gate electrode, 6.7 is a source and drain electrode, and 8 is an insulating layer.
Claims (3)
初反応性ガスを用いてリアクティブイオンエッチングし
、ついでウェットエッチングすることにより鏡面エッチ
ングを行うことを特徴とする半導体結晶のエッチング方
法。(1) A semiconductor crystal etching method characterized by performing mirror etching on the (111)A plane of a III-V compound semiconductor by first reactive ion etching using a reactive gas and then wet etching. .
とを特徴とする特許請求の範囲第１項記載の半導体結晶
のエッチング方法。(2) The method for etching a semiconductor crystal according to claim 1, characterized in that carbon dichloride difluoride is used as the reaction gas.
水素水と水との混液を用いることを特徴とする特許請求
の範囲第１項記載の半導体結晶のエッチング方法。(3) The method of etching a semiconductor crystal according to claim 1, wherein a mixed solution of ammonia water, hydrogen peroxide solution, and water is used in the wet etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22150284A JPS6199337A (en) | 1984-10-22 | 1984-10-22 | Etching method of semiconductor crystal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22150284A JPS6199337A (en) | 1984-10-22 | 1984-10-22 | Etching method of semiconductor crystal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6199337A true JPS6199337A (en) | 1986-05-17 |
Family
ID=16767712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22150284A Pending JPS6199337A (en) | 1984-10-22 | 1984-10-22 | Etching method of semiconductor crystal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6199337A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0590870A2 (en) * | 1992-09-30 | 1994-04-06 | AT&T Corp. | Method of making a buried heterostructure laser |
-
1984
- 1984-10-22 JP JP22150284A patent/JPS6199337A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0590870A2 (en) * | 1992-09-30 | 1994-04-06 | AT&T Corp. | Method of making a buried heterostructure laser |
| EP0590870A3 (en) * | 1992-09-30 | 1994-07-27 | At & T Corp | Method of making a buried heterostructure laser |
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