JPS6199332A - Plasma etching method - Google Patents

Plasma etching method

Info

Publication number
JPS6199332A
JPS6199332A JP22102584A JP22102584A JPS6199332A JP S6199332 A JPS6199332 A JP S6199332A JP 22102584 A JP22102584 A JP 22102584A JP 22102584 A JP22102584 A JP 22102584A JP S6199332 A JPS6199332 A JP S6199332A
Authority
JP
Japan
Prior art keywords
plasma
plasma etching
film
etching
resist film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22102584A
Other languages
Japanese (ja)
Inventor
Riichi Sasaki
佐々木 利一
Satoshi Sudo
須藤 智
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22102584A priority Critical patent/JPS6199332A/en
Publication of JPS6199332A publication Critical patent/JPS6199332A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Abstract

PURPOSE:To enable patterning at a constant speed in high accuracy removing a deposit film by carrying out plasma treatment with oxygen gas in plasma etching. CONSTITUTION:A deposit film is formed by plasma etching to a definite film thickness with a carbon fluoride series gas including hydrogen. Then, the deposit film is removed by plasma treatment with oxygen gas. If the plasma etching and the plasma treatment are carried out alternately, the etching can be advanced at a constant speed. Further, since a resist film can be incinerated by oxygen gas plasma and removed, if the changeover of a treatment time is appropriately adjusted, a resist film pattern is also removed at the time of patterning finish and the simplifying of a photo process can also be possible omitting the process of removing the resist film.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明はプラズマエツチング方法に係り、例えば、半導
体装置の製造プロセスにおける絶縁膜のプラズマエツチ
ング方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a plasma etching method, and for example, to a plasma etching method for an insulating film in a semiconductor device manufacturing process.

半導体装置を製造するウェハープロセスにおいて、半導
体装置を微細化、高集積化するために、ドライエツチン
グが使用されているが、このドライエツチング法の中で
、最近、特にプラズマエツチング方法が重用されるよう
になってきた。
In the wafer process for manufacturing semiconductor devices, dry etching is used to miniaturize and increase the integration of semiconductor devices, but recently, among these dry etching methods, plasma etching methods have been particularly important. It has become.

プラズマエツチング方法とは反応ガスを高周波放電など
によって励起してプラズマ化し、被処理膜に接触させて
、プラズマ中のラジカルとの化学反応によって被処理膜
をガス化して除去する方法で、効率良く、且つ、高精度
にエツチングできる利点がある。
The plasma etching method is a method in which a reactive gas is excited by high-frequency discharge, turns into plasma, is brought into contact with the film to be processed, and the film to be processed is gasified and removed through a chemical reaction with radicals in the plasma. In addition, it has the advantage of being able to be etched with high precision.

しかし、反応ガスの種類によっては、反応生成物が残存
する場合があり、そのような場合のプラズマエツチング
には新規な対策が必要である。
However, depending on the type of reaction gas, reaction products may remain, and new countermeasures are required for plasma etching in such cases.

[従来の技術] 第2図はプラズマエツチング装置の概要断面図で、1は
反応室、2は反応ガス流入0.3は真空排気口、4,5
は対向電極、6は絶縁体、7は被処理試料(半導体基板
) 、 RFは高周波発振器(周波数:13.56MH
z)を示しテイル。
[Prior Art] Fig. 2 is a schematic sectional view of a plasma etching apparatus, in which 1 is a reaction chamber, 2 is a reaction gas inflow, 3 is a vacuum exhaust port, 4, 5
is a counter electrode, 6 is an insulator, 7 is a sample to be processed (semiconductor substrate), RF is a high frequency oscillator (frequency: 13.56MH
z) indicates tail.

このようなプラズマエツチング装置に、第3図18)に
示す工程断面図のような半導体基板を装入して、以下に
説明する反応ガスを用いて、プラズマエツチングを行な
う。
A semiconductor substrate as shown in the cross-sectional view of FIG. 3 is loaded into such a plasma etching apparatus, and plasma etching is performed using a reaction gas as described below.

第3図(a)において、11はn型半導体基板(ウェハ
ー)、12はp型領域、13は二酸化シリコン膜(S’
i02 III) 、 14はレジスト膜パターンを示
し、このレジスト膜パターン14をマスクとして5iO
2111I!13を窓あけする場合には、第2図に示す
エツチング装置にこの半導体基板を装入し、図示のよう
に一方の電極5に半導体基板を載置して、水素を含む弗
化炭素系ガス、例えばトリフロロメタン(CHF a 
)ガスを反応ガス流入口2から導入する。
In FIG. 3(a), 11 is an n-type semiconductor substrate (wafer), 12 is a p-type region, and 13 is a silicon dioxide film (S'
i02 III), 14 indicates a resist film pattern, and using this resist film pattern 14 as a mask, 5iO
2111I! 13, the semiconductor substrate is loaded into the etching apparatus shown in FIG. , for example trifluoromethane (CHF a
) Gas is introduced from the reaction gas inlet 2.

かくして、反応室1の中の減圧度を0.1〜I Tor
r程度にして、両電極4,5の間に高周波電力を印加し
、反応ガスをプラズマ化して、レジスト膜パターン14
から露出している5i02膜13をエツチングする。
Thus, the degree of vacuum in the reaction chamber 1 is set to 0.1 to I Tor.
r, high-frequency power is applied between both electrodes 4 and 5 to turn the reactive gas into plasma and form the resist film pattern 14.
The 5i02 film 13 exposed from above is etched.

[発明が解決しようとする問題点〕 そうすると、第3図(b)に示す工程断面図のように、
5i02膜13がエツチングされ始めるが、一方でレジ
スト膜パターン14と接触したプラズマガスによってデ
ポジット膜15が生成され、例えば膜厚5000人の5
i02膜13を窓あけする場合に、膜厚数100人程フ
チエツチングすると、この析出したデポジット膜15が
表面を覆い、エツチング速度が遅くなって、やがてエツ
チングが進行しなくなると云う問題が起きる。
[Problems to be solved by the invention] Then, as shown in the cross-sectional view of the process shown in FIG. 3(b),
The 5i02 film 13 begins to be etched, but on the other hand, a deposit film 15 is generated by the plasma gas that has come into contact with the resist film pattern 14, and for example, a deposit film 15 with a film thickness of 5,000 mm is formed.
When opening a window in the i02 film 13, if the edge is etched to a thickness of several hundred layers, the deposited film 15 will cover the surface, slowing down the etching speed, and eventually stopping the etching process.

このように、エツチングが不安定になると、パターンニ
ング精度も悪くなり、且つ、このデポジット膜を除去し
なければ、エツチングを行なうことができな(なる。
When etching becomes unstable in this way, patterning accuracy also deteriorates, and etching cannot be performed unless this deposited film is removed.

本発明は、このようなデポジット膜を除去し、一定速度
で高精度にパターンニングするプラズマエツチング方法
を提案するものである。
The present invention proposes a plasma etching method for removing such a deposit film and patterning it at a constant speed and with high precision.

[問題点を解決するための手段] その問題は、水素を含む弗化炭素系ガスによって、レジ
スト膜マスクを設けた被処理試料をプラズマエツチング
する工程において、該プラズマエツチングの途中で、酸
素ガスによるプラズマ処理を行なうようにしたプラズマ
エツチング方法によって解決される。
[Means for solving the problem] The problem is that in the process of plasma etching a sample to be processed with a resist film mask provided with a fluorocarbon gas containing hydrogen, during the plasma etching process, the etching process is performed using oxygen gas. The problem is solved by a plasma etching method that performs plasma treatment.

例えば、水素を含む弗化炭素系ガスによるプラズマエツ
チングと、酸素ガスによるプラズマ処理とを交互に行な
い、レジスト膜マスクの除去と被処理試料の窓開けとが
同時に完了するようにしたプラズマエツチング方法を行
なう。
For example, there is a plasma etching method in which plasma etching using a carbon fluoride gas containing hydrogen and plasma processing using oxygen gas are performed alternately, so that the removal of the resist film mask and the opening of the sample to be processed are completed at the same time. Let's do it.

[作用] 即ち、水素を含む弗化炭素系ガスによって、一定の膜厚
をプラズマエツチングすると、デポジット膜が生成され
る。従って、次に、酸素ガスによるプラズマ処理を行な
って、デポジット膜を除去する。
[Function] That is, when a certain film thickness is plasma etched using a fluorocarbon gas containing hydrogen, a deposit film is generated. Therefore, next, plasma treatment using oxygen gas is performed to remove the deposited film.

かくして、プラズマエツチングとプラズマ処理とを交互
に行なえば、エツチングを一定速度で進行させることが
できる。更に、レジスト膜は酸素ガスプラズマによって
灰化されて取り除かれるから、処理時間の切り換えを上
手に関節すれば、パターンニング終了と同時にレジスト
膜パターンも除かれ、レジスト膜除去の工程を省略して
、フォトプロセス工程を簡単化することも可能になる。
Thus, by alternately performing plasma etching and plasma treatment, etching can proceed at a constant rate. Furthermore, since the resist film is ashed and removed by oxygen gas plasma, if the processing time is properly switched, the resist film pattern will be removed at the same time as patterning is completed, and the process of removing the resist film can be omitted. It also becomes possible to simplify the photoprocessing process.

[実施例] 以下3図面を参照して実施例によって詳細に説明する。[Example] Examples will be described in detail below with reference to three drawings.

第1図(a)〜(dlは本発明にかかる工程順断面図を
示しており、同図(a)は第3図<21)と同様に、n
型半導体基板11にp型頭域12が設けられ、その表面
に被覆したSt O211i13を窓開けするために、
レジスト膜パターン14が形成されている工程途中図で
ある。
FIGS. 1(a) to (dl) show step-by-step sectional views according to the present invention, and FIG. 1(a) is similar to FIG. 3<21).
A p-type semiconductor substrate 11 is provided with a p-type head region 12, and in order to open the St O211i13 coated on the surface of the p-type head region 12,
FIG. 3 is a diagram showing a process in progress in which a resist film pattern 14 is formed.

このような半導体基板を、第2図に示すエツチング装置
に装入し、電極5上に載置して、トリフロロメタンガス
を反応ガス流入口2から流入させる。そうすれば、第1
図山)に示すように、露出した5i02膜13がエツチ
ングされ、その膜厚が500・〜1000人程度エフチ
ング除去されると、デポジット膜15が表面に生成され
、それが表面を覆うようになる。
Such a semiconductor substrate is loaded into the etching apparatus shown in FIG. 2, placed on the electrode 5, and trifluoromethane gas is introduced from the reaction gas inlet 2. Then, the first
As shown in Figure 2), when the exposed 5i02 film 13 is etched and removed by etching to a thickness of about 500 to 1000, a deposit film 15 is generated on the surface and covers the surface. .

次いで、エツチング装置に流入するトリフロロメタンガ
スを止め、次に、酸素ガスを反応ガス流入口2から流入
する。そうすると、第1図(C)に示すように、酸素ガ
スプラズマによってデポジット膜が除去される。その際
、レジスト膜パターン14も表面が一部灰化して除去さ
れる。
Next, the trifluoromethane gas flowing into the etching apparatus is stopped, and then the oxygen gas is introduced from the reaction gas inlet 2. Then, as shown in FIG. 1(C), the deposited film is removed by oxygen gas plasma. At this time, the surface of the resist film pattern 14 is also partially ashed and removed.

このようにして、エツチング装置に流入する反応ガスを
、トリフロロメタンガスと酸素ガスとで、交互に切り換
えてエツチングを進行させる。そうすれば、最終的には
、第1図(d)に示すように、s:o2膜13は窓開け
されて、表面に僅かのレジスト膜パターン14が残存す
ることになるから、このレジスト膜パターン14を酸素
ガスによって灰化して、完全に除去する。
In this way, the etching progresses by alternately switching the reaction gas flowing into the etching device between trifluoromethane gas and oxygen gas. Then, as shown in FIG. 1(d), the S:O2 film 13 will be opened and a small amount of the resist film pattern 14 will remain on the surface. The pattern 14 is incinerated with oxygen gas and completely removed.

このように処理すれば、プラズマエツチングを一定速度
で進めることができ、且つ、窓開は工程でレジスト膜パ
ターンも除去されるため、次のレジスト膜除去工程が不
要になり、フォトプロセスが簡単化される。
By processing in this way, plasma etching can proceed at a constant speed, and the resist film pattern is also removed during the window opening process, making the subsequent resist film removal process unnecessary and simplifying the photo process. be done.

尚、上記はトリフロロメタン(cut、 )ガスをエツ
チング反応ガスとした実施例であるが、本発明はジフロ
ロメタン(CHF2 ’Iガスなど、他の水素を含む弗
化炭素系ガスによるエツチング全般に通用することがで
きる。
Although the above is an example in which trifluoromethane (cut) gas is used as the etching reaction gas, the present invention is generally applicable to etching using other hydrogen-containing fluorocarbon gases such as difluoromethane (CHF2'I gas). can do.

[発明の効果] 以上の説明から明らかなように、本発明によればプラズ
マエツチングが容易に行なえて、パターンニング精度が
向上し、更に、工程の簡単化もできる効果のあるもので
ある。
[Effects of the Invention] As is clear from the above description, according to the present invention, plasma etching can be easily performed, patterning accuracy can be improved, and the process can be simplified.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜((旧よ本発明にかかるプラズマエツチ
ング方法の工程順断面図、 第2図はプラズマエツチング装置の概要断面図、第3図
(a)、 (b)は従来のプラズマエツチング方法の工
程順断面図である。 図において、 lはプラズマエツチング装置の反応室、2は反応ガス流
入口、 3は真空排気口、4.5は電極、    RF
は高周波発振器、7は被処理試料、 11はp型半導体基板、 12はn型領域、13は5i
02膜、     14はレジスト膜パターン15はデ
ポジット膜 を示している。 σ             D L へへ υ                 ℃νV
Figures 1(a) to ((old) are cross-sectional views of the plasma etching method according to the present invention in the order of steps; Figure 2 is a schematic cross-sectional view of a plasma etching apparatus; Figures 3(a) and (b) are conventional 1 is a step-by-step sectional view of an etching method. In the figure, l is a reaction chamber of a plasma etching device, 2 is a reaction gas inlet, 3 is a vacuum exhaust port, 4.5 is an electrode, and RF
is a high frequency oscillator, 7 is a sample to be processed, 11 is a p-type semiconductor substrate, 12 is an n-type region, 13 is 5i
02 film, 14 is a resist film pattern 15 is a deposit film. σ D L to υ ℃νV

Claims (2)

【特許請求の範囲】[Claims] (1)水素を含む弗化炭素系ガスによつて、レジスト膜
マスクを設けた被処理試料をプラズマエッチングする工
程において、該プラズマエッチングの途中で、酸素ガス
によるプラズマ処理を行なうようにしたことを特徴とす
るプラズマエッチング方法。
(1) In the process of plasma etching a sample to be processed with a resist film mask provided with a fluorocarbon gas containing hydrogen, plasma treatment with oxygen gas is performed during the plasma etching. Characteristic plasma etching method.
(2)上記工程において、水素を含む弗化炭素系ガスに
よるプラズマエッチングと、酸素ガスによるプラズマ処
理とを交互に行ない、レジスト膜マスクの除去と被処理
試料の窓開けとが同時に完了するようにしたことを特徴
とする特許請求の範囲第1項記載のプラズマエッチング
方法。
(2) In the above process, plasma etching with hydrogen-containing carbon fluoride gas and plasma treatment with oxygen gas are performed alternately so that the removal of the resist film mask and the opening of the sample to be processed are completed at the same time. A plasma etching method according to claim 1, characterized in that:
JP22102584A 1984-10-19 1984-10-19 Plasma etching method Pending JPS6199332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22102584A JPS6199332A (en) 1984-10-19 1984-10-19 Plasma etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22102584A JPS6199332A (en) 1984-10-19 1984-10-19 Plasma etching method

Publications (1)

Publication Number Publication Date
JPS6199332A true JPS6199332A (en) 1986-05-17

Family

ID=16760306

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22102584A Pending JPS6199332A (en) 1984-10-19 1984-10-19 Plasma etching method

Country Status (1)

Country Link
JP (1) JPS6199332A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63124527A (en) * 1986-11-14 1988-05-28 Nec Corp Manufacture of semiconductor device
EP0933802A4 (en) * 1996-11-14 1999-10-27 Tokyo Electron Ltd Process for the production of semiconductor device
JP2020136473A (en) * 2019-02-19 2020-08-31 株式会社東芝 Method for manufacturing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63124527A (en) * 1986-11-14 1988-05-28 Nec Corp Manufacture of semiconductor device
EP0933802A4 (en) * 1996-11-14 1999-10-27 Tokyo Electron Ltd Process for the production of semiconductor device
US6727182B2 (en) 1996-11-14 2004-04-27 Tokyo Electron Limited Process for the production of semiconductor device
JP2020136473A (en) * 2019-02-19 2020-08-31 株式会社東芝 Method for manufacturing semiconductor device

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