JPS619763A - Picture processing system - Google Patents

Abstract

PURPOSE:To attain the high-speed affine conversion by transferring the picture element values of a processor array to the unit processors corresponding to the original coordinates in parallel to each other every grid point. CONSTITUTION:There are (NXN) units of unmit processors 1 provided corresponding to the grid points of a digital picture. Each processor 1 applies the adverse affine conversion to the original coordinates of the grid point corresponding to said processor 1. Thus the desired coordinates can be obtained. Then the original coordinates is transferred to the unit processor corresponsding to said deisred coordinates. Receiving the original coordinates, the relevant processor 1 transfers the picture element value to another processor 1 corresponding to the original coordinates in parallel and every grid point. Therefore the number of processors 1 can be reduce down to (2XN) units within a route where data reach the processor 1 corresponding to the original coordinates from the processor 1 corresponding to the desired coordinates.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image processing method for performing digital image processing.

[Prior art]

Conventionally, in this type of image processing method, in the process of applying affine transformation to a digital image, the affine transformation is A, the coordinate value of the grid point of the digital image is P, and the coordinate value q is calculated before and after the transformation. Each pixel value is d (q
) and d'(q), then d"(q)←a(r(4P
)) ......(1) can be written as,
However, the arrow indicates that the right side of the arrow is substituted for the left side of the arrow, A-1 indicates the inverse transformation of A, and f (q) is q
Shows the results of digitization operations such as rounding and truncation. In addition, in actual image processing,
There are upper and lower limits for the coordinate values of the image to be processed. The upper and lower limits of the X and y coordinates are respectively Xmas
, Xm1n, Ymas, )'min and the X and y coordinates of the coordinate value q are respectively QX I Qy, then the above d(Q) needs to satisfy the condition of the following formula C2).

Therefore, if the condition of the above equation (2) is not satisfied, it is not defined, so it can be defined as a special value (for example, O) indicating that the value is not defined.

Now, in the conventional image processing method, the process shown in the above equation (1) is sequentially performed on all grid points of the image. FIG. 1 is a flowchart showing an example of a conventional image processing method. In Figure 1, to simplify the explanation, Xm1n = ymin = 0°XmaX ""
The increments of YmaX "" N 1 + X + 7 are set to 1. As shown in the figure, in 81 and N2, the initial value O is substituted for variables X and y representing lattice points. In N3, data d (x.

xl and yl, which are the coordinates of the grid point where y) is to be stored, are calculated. At N4 and N5, it is determined whether xl and yl are between 0 and N-1, which are the upper and lower limits of the coordinate values. If the result of the judgment is true, d (
x r y ) to d(xi, yl), and if it is false, d(
i, yl). At N8, y is increased by 1 in order to process the next grid point. In N9,
It is determined whether y exceeds the upper limit N-1, and if it does not exceed the upper limit, the process returns to N3. If it exceeds the upper limit, X is incremented by 1 in S10, and it is determined in SII whether or not X exceeds the upper limit N-1. N if X does not exceed the upper limit N-1
2, and if it exceeds, the process ends. As is clear from the above description, each step of N3, 84°N8, and N9 is executed only N2 times.

Also, the number of times it is determined to be true or false in N4 is
Let 4f be the number of times S5 is determined to be true or false, and let f be N5. The following relational expressions hold for the number of times N6 and S7 are executed: , k, and 7.

(ks = k4t = N - k4f Therefore, k, , k6. The sum of k, is ks
Therefore, it is clear that image processing as shown in Fig. 1 consumes processing time proportional to the total number of grid points, that is, N2. , had the disadvantage that it was not possible to perform high-speed affine transformations.

[Summary of the invention]

This invention was made with the aim of improving the drawbacks of the conventional ones as described above, and uses a processor Φ array consisting of a group of unit processors corresponding to a lattice point on a two-dimensional coordinate plane. Each unit processor is
Apply inverse affine transformation to the original coordinates of the grid point corresponding to the corresponding unit processor to obtain the target coordinates, transfer the original coordinates to the unit processor corresponding to the target coordinates, and transfer the original coordinates to the received target coordinates. The corresponding unit processor is
The present invention provides an image processing method that can realize high-speed affine transformation processing by performing the process of transferring the pixel value to the unit processor corresponding to the original coordinates in parallel for each grid point. be.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing an image processing method according to an embodiment of the present invention. In the figure, 1 is a unit processor, and NX8 corresponds to the grid points of the digital image.
are arranged. Note that the unit processor 1 at the bottom left in Figure 1 is set to X = Xmin, Y ``”')'min, and the unit processor 1 at the top right is x''
Each corresponds to x. Signal lines 2 and 3 connect the unit processors 1, and connect adjacent unit processors 1 in the X and y directions, respectively.

Furthermore, unit processors 1 corresponding to the upper and lower limits of the X and y coordinates are also interconnected via each signal line 2 or 3. 4 control processors, unit processor 1
It is capable of inputting data to and receiving data from a processor array consisting of a set of processors.

When inputting data from the control processor 4 to the processor array, x=X via the signal line 5 and selector 6.
ml. , y=)'min K data is input to the corresponding unit processor 1. Selector 6 is X=Xmax
, )' = data sent from the unit processor 1 via the signal line 2 corresponding to Ymax and the control group are selected. The configuration of the control processor 4 and selector 6 is as follows:
Since it has no direct relation to this invention, detailed explanation thereof will be omitted.

FIG. 3 is a diagram showing the configuration of signal lines connecting each unit processor in the image processing method shown in FIG. 2. The same reference numerals as in FIG. Explanation will be omitted. The direction of signal propagation is indicated by the arrow in the figure for each signal line. In the figure, 2a and 3a are signal lines for transferring data, and data is transferred from a small unit processor 1 with a small X and y coordinate to a large unit processor 1. Also, X”Xm1n
+'/=Ymin unit processor 1 and X=X
The unit processor 1 of m3z + Y=YmaX can transfer data with the control processor 4, as described above. In this way, the data transferred via each signal @2a and 3a includes the pixel value of the digital image, the coordinate value, the matrix that defines the affine transformation, and the unit processor IK.
There are instructions and control information to be given. 2b and 3b are 1-bit signal lines (REQX and REQX) requesting data transfer.
EQY), and when the value of the signal line is 11'', data is transferred from the unit processor 1 with the smaller X and y coordinates to the unit processor 1 with the larger one. 2C and 3C are 1-bit signal lines (RPLYX and R
Data is transferred from the unit processor 1 with larger X and y coordinates to the smaller unit processor 1 (referred to as PLYY). Each RPLYX2c and RPLYY3c is 11"
When , each REQX2b and REQY3b are 11
”. 2d and 3d have a value of 11
”, a 1-bit signal #(
CMPLX and CMPLY), and data is transferred from the unit processor 1 with the smaller X and y coordinates to the larger unit processor l. The control processor 4 determines that X=X
max, Y=unit processor 1 corresponding to Ymax
By receiving CMPLX2d of
You can know when the entire play process is complete.

Figures 4 (a) and (b) are diagrams showing the general format of data transferred via the signal line in the image processing method shown in Figure 2, and the types of each data and their contents. It is a diagram. In the 41st S9(a), 8 is a part (referred to as TAG) indicating the type of data, and 9 is a part (referred to as BODY) indicating the data value. Figure 4(b)
As shown in , when TAG8 has the value iMTXJ, BO
DY9 is a value of a matrix that defines affine transformation, and data in this case is transmitted to all unit processors 1.

When TAG8 has the value IPRDJ, BODY9 is the coordinates (called target coordinates) obtained by applying the inverse affine transformation to the coordinates of unit processor 1 (called original coordinates), and in this case, the data is transferred to the adjacent unit processor 1. communicated.

When TAG8 has a value of l'FWDJ, BODY9 is extracted with the target coordinates and original coordinates, and the data in this case is sent to the unit processor 1 corresponding to the target coordinates.

When TAG8 has the value rBWDJ, BODY9 is the pixel value of the original coordinates and the target coordinates, and the data in this case is sent to the unit processor 1 corresponding to the original coordinates. TAG8
When is a value of IcMPJ, BODY9 is the pixel value of the target coordinate, and the data in this case is sent to the unit processor 1 corresponding to the original coordinate.

FIG. 5 is a block diagram showing an example of the internal configuration of one unit processor in the image processing method of FIG.
Since the same reference numerals as in FIGS. 2 and 3 represent the same or corresponding components, their explanations will be omitted. In the figure, ]O
a and 10b are registers (referred to as IBX and IBY) that store data transferred from adjacent unit processors 1 via respective signal lines 2a and 3a. lla and l
lb is a register (OB
X and OBY). 12 is a register (referred to as P) that stores the original coordinates. Reference numeral 13 is a register (referred to as DS) that stores pixel values at the coordinates of the unit processor 1 before being subjected to affine transformation. 14 is a register (referred to as DD) that stores the pixel value of the coordinates of the unit processor 1 after being subjected to affine transformation. 15 is a switch circuit (referred to as SW) that controls data transfer between each IBX 10a and IBY 10b;
, IBY10b.

0BX11a, 0BY11b, P 12, DS 13
and DD14, each signal line 16a, 16b
, 17a, 1.7b and 18-20. 21 is a circuit (referred to as CNT) that controls the operation of the unit processor 1, and this CNT 21 controls the data transfer between each unit processor 1 via each signal a2b to 2d and 3b to 3d, and each IBX 10a, IB
Y10b, 0BX11a, 0BY11b, P 12 ,
DS13.

Controls the components of the DD 14 and SWI 5.

In addition, in order to simplify the explanation, CNT21 and each IBX1
0a, IBY10b, 0BXIla, 0BY11b
, Pl 2°DS13. The control signal line between DD14 and 5W15 is omitted.

Next, the operation of the image processing system which is an embodiment of the invention described above will be explained. The overall processing by this image processing method is performed in the following manner.

In step A, the ATG 8 from the control processor 4
Enter the data for XJ. This data is sequentially transmitted to all unit processors IIC.

Step A2: Each unit processor l is l'M T
The target coordinates are calculated from the data of J and the original coordinates of the unit processor 1.

Step A3 If the target coordinates calculated in step A2 exceed the upper or lower limit of the X or y coordinates, the unit processor 1 goes to step A7.

Step A4 and Ti at the target coordinates calculated in step A2.
Adjacent unit processor 1 with IPRDJ of O2
Transfer to.

Step A5 The unit processor 1 whose target coordinates transferred in step A4 match the target coordinates of the unit processor 1 itself goes to step A7.

Step 86 2 target coordinates and original coordinates 1cTAG8 1FW
Send it out with a DJ attached.

Step A7: Sequentially transfer the rFWDJ data to the unit processor IK corresponding to the target coordinates.

Step A8: When the target coordinates of the 1FWDJ data and the unit processor 1's own coordinates match, the unit processor 1 matches the original coordinates of the "FWD" data and the unit processor 1
The pixel value held by TiO2(D[BWDJ) is attached and sent.

Step A9: Sequentially transfer the data of IBWDJ to the unit processor IK corresponding to the original coordinates.

Step A10: The unit processor 1 whose original coordinates of the data of iBwDJ and the original coordinates of the unit processor l itself match takes the pixel value of the data of l'BWDJ and inputs it. Further, the pixel value is attached with rcMPl of TiO2 and transferred to the adjacent unit processor IK.

Step A11: If the unit processor 1 that received the data of fcMPJ is the unit processor 1 that satisfies the condition of step A5, it takes in the pixel value of the data of l'cMPJ and sends it to the adjacent unit processor IK.

Step A12: The unit processor 1 that satisfies the conditions of each step A3 and step A10 or step All,
Each CMPLX transferred from the adjacent unit processor 1
If the values of 2d and CMPLY3d are both 111, set each CMPLX2d and CMPLY3d to I'lJ Ic
and send it.

Step A 13: x:x, nax I Y='/
CMPLX2 sent from unit processor 1 of max
The control processor 4 detects that d has become 11'' and knows that the process is complete. Note that among the above-mentioned processes, each step A4. A5. AIO and All occur when many unit processors 1 have the same target coordinates due to the influence of digitalization. This is a process to avoid data congestion around the unit processor l corresponding to the target coordinates. Furthermore, the above-described processing is executed in parallel in each unit processor 1.

Next, a method of data transfer in each unit processor 1 will be explained. To simplify the explanation, it is assumed that K and data are transferred from the X direction via the signal line 2a. Further, it is assumed that TaO2 of the data is lFWDJ and sb, and the target coordinates of the data do not match the coordinates of the unit processor 1.Data transfer is performed in the following manner.

Step BI: Data is set on the signal line 2a from the adjacent unit processor 1, and REQX2b is set to 11''.

Step B2: Set data 1klBX10a to 0 Step B3: If the X component of the target coordinates of the data matches the X component of the coordinates of the unit processor 1, step B6
go to.

Step B4: @RPL from adjacent unit processor 1
If YX2c is IOJ, set RPLYXZc to 10'' and return to step B4.

Step B6: RPLYY3c and REQY3b
and 0BYI l b, each step B4 and B
Perform the process in step 5.

Next, a description will be given of how each unit processor 1 performs the processing in steps A1 to A13 described above.

Each unit processor 1 can take the following eight states.

State 1: When rM T XJ data is input in the initial state, the target coordinates are calculated accordingly.

If the result exceeds the upper or lower limit of the X or y coordinate, set DDI4 to an appropriate value (for example, IcJ) and proceed to state 8. Otherwise, TaO2 at the target coordinates
IPRDJ is attached and output to the adjacent unit processors 1 in the X and X directions.

The coordinates of unit processor 1 are X = Xmin or Y = Y
mi.

If so, go to state 3, otherwise go to state 2.

State 2: x or adjacent unit processor 1 in the X direction
"When PRDJ data is input, its target coordinates are compared with the target coordinates of unit processor 1. If the target coordinates input from the X direction and the target coordinates of unit processor 1 match, the process advances to state 5, If the target coordinates input from and the target coordinates of unit processor 1 match, state 6 is reached.
If not, go to state 3.

State 3: T to the target coordinates and original coordinates of unit processor 1
Output with 1FWDJ of aO2 attached and go to state 4.

4: 1-BWDJ data is input,
If the target coordinates match the original coordinates of the unit processor 1, the pixel value is set in the DD 14 and the process goes to state 7.

5: From unit processor 1 to IC in X direction
When the data of “MP” is input, the pixel value is transferred to DD14.
and go to state 7.

State 6: From unit processor 1 in the X direction □IcMP
When the data of J is input, the pixel value is set in DD14 and the process goes to state 7.

State 7: Value of DD14 1c T A G 8 Q
It outputs with l-CMPJ attached and goes to state 8.

State 8: When “1” is input from CMPLX2d and CMPLY3d, CMPLX2d and CMPLY
Outputs ``11'' to 3d.

In any of the above states, if the data of rFWDJ or l'BWDJ is input and the target coordinates match, the original coordinates of the data of 1-FWDJ and DS13
The I-BWDJ of TaO2 is added to the pixel value held in the pixel value and output.

As described above, according to the image processing method according to the present invention, the data of l'l''WDJ is output in state 3, and the data is transferred to the original coordinates again via the unit processor l corresponding to the target coordinates. The number of unit processors 1 to be passed through before reaching the unit processor 1 corresponding to 1 is 2XN at most. The number of unit processors 1 is N.

Therefore, in the process of data transfer, each signal fi
If we exclude the waiting time that occurs when a plurality of data items 2a and 3a are shared at the same time, the processing time for affine transformation becomes proportional to NK. In the image processing method VC according to the present invention, when a large number of unit processors 1 have the same target coordinates as described above, K, the unit processor 1 that actually outputs the data of l'-FWDJ
The number of affine transformations can be performed in processing time very close to the reduced time.

In the above embodiments, a specific device configuration example has been described, but it goes without saying that the present invention is not limited to the above-described device configuration example.

〔Effect of the invention〕

As explained above, the present invention uses a processor array consisting of a group of unit processors corresponding to grid points on a two-dimensional coordinate plane in image processing method (C), and each unit process of this processor array is Apply inverse affine transformation to the original coordinates of the grid point corresponding to the corresponding unit processor to obtain the target coordinates, transfer the original coordinates to the unit processor corresponding to the target coordinates, and transfer the original coordinates to the received target coordinates. Since the corresponding unit processor transfers the pixel value to the unit processor corresponding to the original coordinates for each grid point in parallel, the image processing speed is reduced compared to this type of conventional example. This has the excellent effect of being able to perform affine transformation at extremely high speed.

[Brief explanation of the drawing]

FIG. 1 is a flowchart diagram showing an example of a conventional image processing method, FIG. 2 is a block diagram showing an image processing method according to an embodiment of the present invention, and FIG. 3 is a flowchart diagram showing an example of a conventional image processing method. , Figures 4(a) and 4(b) are diagrams showing the configuration of signal lines connecting each unit processor, respectively.
FIG. 2 is a block configuration diagram showing an example of the internal configuration of one unit processor in the image processing method shown in the figure. In the figure, 1... unit processor, 2.2a to 2d
, 3.3a-3d, 5, 7.16a, 16b, 17a. 17b, 18-20...signal line, 4...control processor, 6...selector, 8...portion indicating the type of data (TAG), 9...portion indicating the value of the data (BODY), 10as10b, lla, l
lb, 12 to 14-registers, 15... switch circuits (SW), 21... circuits (CNT') that control the operation of the unit processor 1. In each figure, the same reference numerals indicate the same or equivalent parts. Applicant: Director of the Agency of Industrial Science and Technology Hirobe Kawada Figure 1 Figure 3 Figure 4 (a) (b) Procedural amendment (voluntary) January 23, 1920

Claims (1)

[Claims] In the process of performing affine transformation on a digital image in which digitized pixel values correspond to grid points on a two-dimensional coordinate plane, this process is performed by a unit processor group corresponding to the grid points on the two-dimensional coordinate plane. and in the processing, each unit processor of the processor array performs an inverse transformation of the affine transformation on the original coordinates of the lattice point corresponding to the unit processor to obtain the target coordinates. and transfers the original coordinates to a unit processor corresponding to the target coordinates, and the unit processor corresponding to the target coordinates that received the original coordinates transfers the pixel value to the unit processor corresponding to the original coordinates. and means for transferring the original coordinates and pixel values in parallel via each of the unit processors.