JPS6196595A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To execute the reading action and the refreshing action independently by installing respective word line/bit line for read only/for refreshing only/for write only to a memory cell. CONSTITUTION:A word line WLa corresponding to a refreshing address in accordance with a counter value of the address counter in a control circuit 4 is set to 'H' at the time of refreshing a memory cell 16, a line is selected, a transistor Q1 is connected and a charge of a memory node N is read to a bit line BLb. A change of the electric potential of the line BLb is sent through a sense amplifier of a read/write circuit 15 to the line BLb, and the electric potential of the node N is refreshed. The writing is executed in the same manner. On the other hand, at the time of reading, a line WLa is set to 'H' by the output of a decoder 12, and an electric current of a linear pass of Q3 and Q2 is read by the shape of a signal of a line BLa. As this result, except when a line WLb is 'H' and the charge of the line BLb flows into a node N, the reading can be optionally executed even during the refreshing action.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a dynamic semiconductor memory device, and particularly to its refresh operation.

[Technical background of the invention]

2. Description of the Related Art Conventionally, a dynamic semiconductor memory device (dynamic RAM), which stores all information by accumulating charge in a capacitive element, is configured as shown in FIG. 5, for example. In the figure, WL is a word line, BL is a bit line, and memory cells 11 are located at the intersections of these word lines WL and bit lines BL.
will be placed. The memory cell 11 has one end connected to the bit line BL, and a data transfer layer transistor Q1 connected to the word line WL at one end (e-) and controlled to be conductive.
and a storage capacitor C! connected between the other end of this transistor Ql and the reference power supply vR! It is composed of.

In the above configuration, the write operation is as follows.

It is done as follows. First, the transistor Q1 is made conductive by setting the word line WL to a high level (@H" level) only in the selected row. For writing '01, set the bit line BL to the ground potential v5g. Yoshi memory memory k 117) /-do N v88
When writing ``0''b to the storage capacitor C1, the bit line BL is set to the 1H'' level, the storage node N is set to the vIK potential, and ``1'' information is written.

On the other hand, reading is performed as described below. That is, the bit line BL is charged to a predetermined potential in advance, and then the word line WL is set to ``H#''.
The signal is set to H# level and the transistor Qs t- is made conductive. As a result, the charge QN on the storage node N and the charge Q□ on the bit line BL are redistributed, and the potential on the bit line BL changes slightly depending on the stored information. This fluctuation is detected by a detection amplifier and amplified to a large amplitude signal according to the information of 10m or Qljl that was written down to obtain a readout output, and the bit line BL is again changed to vss or @H.
By driving the potential of the storage node N to the level v
Refresh is performed by setting the potential to 8B or V□.

[Problems with background technology]

By the way, in the dynamic RAIM mentioned above,
In a state of deep information retention, transistor Q! becomes non-conductive,
Storage node N becomes floating.

However, the voltage at the storage node N changes due to leakage current, and information is lost over time.

To prevent this, periodically read the above,
It is necessary to perform a rewrite (refresh) operation.

During such an operation, a normal read operation of any address cannot be performed, and must be performed after waiting for the completion of refresh. As described above, a dynamic RAM configured with one transistor and one capacitor has the advantage of high density and low cost, but has the disadvantage that the read operation is hindered by the refresh operation.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to provide a dynamic semiconductor memory device configured to perform read operations and refresh operations independently, and in which the read operation is not hindered by the refresh operation. [Summary] That is, in the present invention, in order to achieve the above object, a word line and a bit line dedicated for reading information, and a read line for refreshing,
By providing write-only word lines and bit lines, the structure is such that read operations and refresh operations can be performed independently.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, wLa and BLIL are a read-only word line (row selection line) and a bit line, respectively; a read address decoder 12 is connected to the word line WLa, and a read circuit 13 is connected to the bit line BLa. ◎ Also, WLb and BLb are a word line 9 and a bit line for reading and writing for refreshing, respectively.The word line wLb has an address control circuit 14 for writing and refreshing, and the bit line BLb has a line for refreshing. read/write circuits 15 are connected to the read/write circuits 15, respectively. The bit line BLb is
It is connected to one end of the information transfer transistor Q1, the other end of this transistor Q1 is connected to one electrode of the storage capacitor C1, and the dirt is connected to the word line wL.
connected to b. The other electrode of the capacitor C1 is connected to the reference power supply VB, and the connection point (storage node N) between the capacitor C1 and the transistor Q1 is connected to ff-) of the transistor Q2. One end of this transistor Q2 is connected to the power supply line V (for example, ground potential), and the other end is connected to the bit line BLa through a transistor 3t- whose other end (r-) is connected to the word line WLa. . The transistors Q1 to Q3 and the transistor C1 constitute one memory cell 16, and such memory cells are arranged in row and column directions to constitute a memory device.

Next, the operation of the above configuration will be explained. The refresh operation of memory cell 16 is performed as follows. First, the word line WLa corresponding to the flexible address is
t″″ is set to H# level to select a row and make transistor Qs′ conductive. By this, storage node N
The charges are read out to bit line BLb. This change in the potential of the bit line BLb is amplified by the detection amplifier circuit of the refresh read/write circuit 15, and a large amplitude signal corresponding to the read information is returned to the bit line BLb, thereby increasing the potential of the storage node N. will be refreshed. In addition, the pledge is also performed in the same manner as the above-mentioned refresh.

On the other hand, in a normal read operation, the word line WLa is set to a high potential by the read address decoder 12, thereby making the transistor Qst conductive. At this time, transistor Q! are in a conductive or non-conductive state depending on the potential of storage node N, so that transistors Q3. The direct current/bus current of Q2 is read out in the form of a signal on the bit line BLa. The conductance of the transistor Q2 is determined by the potential of the storage node N. Therefore, except when the word line wtb is at the "H# level" and the charge on the bit line BLb flows into the node N, the conductance of the transistor Q2 is determined by the potential of the storage node N. can also be read freely.

Further, the problem when the charge on the bit line BLb flows into the storage node N can be prevented as follows. That is, in the refresh operation, the potential of the word line wLb is initially raised from QV to about 1.5 to 2 times the threshold voltage V of the transistor Q1 or Q2. By doing so, even if the potential of the storage node N is Ov, the potential of the node N will only rise to about 0.5 to 1 times the threshold voltage vT even if the transistor Q1 becomes conductive.

Therefore, transistor Q2 is not conductive and bit line BLa
No problem occurs no matter what timing the read operation is performed from the side.

Then, the minute signal on the bit line BLb is amplified by the sense amplifier of the refresh read/write circuit 15, and the word line wLb is raised from the intermediate potential to a higher potential, and then the bit line BLb is connected to the ground potential or the power supply voltage. Write all potentials and perform a refresh operation. Since the amplitude of the word line wLb is initially small, refresh reading cannot be performed at high speed, but this is not a particular problem since refresh is performed once every several milliseconds or more. Although one end of the storage capacitor C1 is connected to the reference power supply vR in FIG. 1, it may be connected to the power supply line v8.

According to such a configuration, the read operation in the dynamic semiconductor memory device is hardly hindered by the refresh operation. Moreover, since normal readout is a method of detecting all d current values, the S/N is extremely high.
The ratio is high, making it possible to apply it to larger capacity memories compared to conventional charge readout methods.

FIG. 2 shows another structure 13'l of the memory cell of the semi-η-plane storage device according to the present invention. One end of the information transfer transistor Q1 is connected to the pin line BLb, the other end is connected to one electrode of the storage capacitor C1 and the gate of the transistor Q4, and the r-to is connected to the word line M. connected to b. The other electrode of the capacitor C1 is connected to the word line WLa. Further, one end of the transistor Q4 is connected to the bit line BLa,
The other end is grounded to form a memory cell.

In such a configuration, depending on the fourth position of word line WLa,
Due to the capacitive coupling between the storage capacitor C1, the parasitic capacitance (t) between the storage capacitor C1, the transistor Q4 (r-), and the source, the potential of the storage node N changes.

As a result, the conduction resistance of the transistor Q4 changes, so that the bit voltage changes depending on the potential of the node N.

The potential of the line BLa changes and the entire stored information can be exposed. In this case, the potential width of the output level is determined according to the setting of the capacitance ratio of each capacitor/mother capacitor C1+C2. Note that refreshing and writing may be performed in the same manner as in the circuit shown in FIG.

3 and 4 respectively show other configuration examples of memory cells in the semiconductor memory device of the present invention.
OS) Information is read out using the substrate bias effect of the transistor.

One end of the information transfer transistor Qr in FIG.
Bit line BLb is connected to K, and the other end is connected to transistor Qs.
r-) of the word line W, and the gate 9- is connected to the word line W
Connected to Lb. One end of the transistor Qs is connected to a reference power supply vR (for example, IAvCc), the other end is connected to a bit line BLa, and the packed dirt is connected to a word line WLa.

In the above configuration, the potential of the word line WLa is set to O.
When the voltage changes from V (non-selected) to 1/2 VCc (selected), the on-voltage of transistor Q5 changes due to the substrate bias effect. When the word line WLa is at 070, the transistor QS is maintained in an off state, and when the word line WLa is at the 1/2vcC level, the transistor Q5 is
The conduction resistance of changes. By this, bit & IBL
The stored information can be read from a. The refresh and write operations are similar to those shown in FIG. 1, and information is stored by accumulating charge in the capacitance between the date and source of the transistor Qs.

On the other hand, one end of the information transfer transistor Q1 in FIG. 4 is connected to the bit line BLb, the other end is connected to the pack e-) of the transistor Q6, and the dart is connected to the word line WLbK. One end of the transistor Q6 is connected to the reference power supply VIL (for example, 1/2 Vcc), the other end is connected to the bit line BLa, and the date is connected to the word line JJLK.

In the above configuration, the potential of the word line WLa is set to Q
By changing from V (non-selected) to vcc (selected), the transistor Qs' can be turned on/off. When this transistor Q6 is in the on state, the substrate bias of the transistor Q6 is changed according to the potential of the storage node N. The effect changes, which changes the conduction resistance of transistor Q6. Therefore, if the potential of node N is now ov~l/2vcc, the potential from bit line BLa is 1/2vcc~l/2vcc.
A signal with a potential amplitude up to vcC is obtained as read information. Refresh and write operations are the same as in the case of FIG. 1, and refresh and write operations are performed by accumulating charge in the capacitance between the pack date (substrate) and source of transistor Q6.

〔Effect of the invention〕

As described above, according to the present invention, since the read operation and the refresh operation are performed completely independently, a dynamic semiconductor memory device in which the read operation is not interfered with by the refresh operation can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a semiconductor memory device according to an embodiment of the present invention, FIGS. 2 to 4 are circuit diagrams for explaining other embodiments of the invention, and FIG. The figure is a diagram for explaining a conventional semi-quadramid storage device IT. 12... Read address decoder, 13... Read circuit, 14... Address control circuit for writing and refresh 1, 15... Read/write circuit for refreshing, 16... Memory cell, wLb...first word line, BLb...first bit line, WLa...
Second word line, BLa...second bit line, Q. . . . Transistor for information transfer, C1 . Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4 Figure R Figure 5

Claims (1)

[Claims] In a dynamic semiconductor memory device that stores information by storing charge in a capacitive element, refresh writing means performs refreshing and writing of information by injecting charge into a storage node of a memory cell or extracting charge from a storage node. , a first word line that selects a storage cell based on the output of the refresh writing means;
A first bit line, a voltage-current conversion means for converting the voltage of the storage node storing the charge into a current corresponding to the voltage, and information from the storage node of the storage cell based on the output of the voltage-current conversion means. A semiconductor memory device comprising a second word line and a second bit line for reading.