JPS6194485A - Convergence correcting circuit for projector - Google Patents

Abstract

PURPOSE:To prevent mis-convergence even when the fixed installation of a projector and the suspension from ceiling are changed by reversing generation sequence of the reading address signal supplied to a correcting memory in accordance with the control signal showing an installation condition of the projector. CONSTITUTION:In an address generating circuit 50, an action is controlled in accor dance with a fixed installation suspension from ceiling changeover control signal CONT, and a generating part 51, respective different address data are loaded through a selector 52 in accordance with the fixed installation/suspension from ceiling state, then the clock is counted up or down and a horizontal address signal is supplied to a corrected quantity memory 20. In the generating circuit 55, respective different address data are loaded through a selector 56 in accordance with the fixed installation/ suspension from ceiling condition, the clock is counted up or down and a vertical address signal is supplied to the memory 20. Thus, a reading direction of the conver gence correcting quantity data from the memory 20 in accordance with the difference of the scanning direction due to the installation condition of the projector is reversed, and even when the scanning direction is reversed, the same convergence correction is executed concerning the same position.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a convergence correction circuit for a projector, and is particularly suitable for application to a digital convergence correction circuit for a projector that can be used in a side-mounted manner such as a stationary or ceiling-mounted projector. It is something.

[Conventional technology]

In a cathode ray tube (CRT) of a projector, multiple electron beams (for example, R signal, G
signals (for B signals) do not necessarily converge at one point on the screen of a CRT, resulting in misconvergence. The amount of misconvergence increases from the center to the periphery of the tube surface, and also in the periphery, the magnitude differs at each of the four corners.

If this misconvergence is not corrected, the edges of the image will shift and the screen will become difficult to see. Therefore, conventionally, projectors used for stationary installation are equipped with a convergence correction circuit 10 as shown in FIG.

In FIG. 2, the correction amount memory stores, for example, convergence correction amount data for each pixel for l fields, and the clock signal CLKIC of the excavation circuit 21
Convergence correction data at predetermined addresses are read out in sequence in synchronization.

The address generation circuit (9) receives data from the correction amount memo I720! j! :Generates a 4-digit read address signal, for example, as shown in FIG. 3, for reading. Here, the lower two digits of the read address signal indicate a horizontal address signal HAD corresponding to the horizontal direction of the CRT tube surface, which is generated by a horizontal address generation circuit 31 having a counter configuration. Further, the upper two digits of the read address signal indicate a vertical address signal VAD corresponding to the vertical direction of the CRT tube surface, and are generated by a vertical address generating circuit 32 having a counter configuration.

The horizontal address generation circuit 31 receives the horizontal synchronizing signal H8YN (l load command signal) separated from the video signal and receives the start address data H8A (for example, content is "00") stored in the horizontal start address storage circuit 33. In this way, each time the clock signal CLK arrives, the count contents are increased and the horizontal address signal H is loaded.
It is given to the correction amount memory as AD.

The vertical address generation circuit 32 receives the vertical synchronization signal VSYNC separated from the video signal as a load command signal, and is loaded with the start address data VSA (for example, roOJ & content) stored in the vertical start address storage circuit. Each time the horizontal synchronization signal H8YNCk is received as a clock signal, the count contents are increased and the correction amount memo 1J20VC is used as the vertical address signal VAD.
give.

The correction amount memo I720 reads the convergence correction amount data CAD at the address indicated by the horizontal address signal HAD and the vertical address signal VAD and provides it to the digital-to-analog conversion circuit 22, and the digital-to-analog conversion circuit η converts this convergence correction amount data cAD into an analog signal. and feed it to the convergence coil.

According to the circuit 10 of FIG. 2, the horizontal address generation circuit 31 and the vertical address generation circuit 32 are synchronized with the scanning of the CRT.
By the addresses HAD and VAD generated in
Convergence correction amount data CAD for pixels at each scanning position is output from the correction amount memo IJ20. In this way, the misconvergence amount is corrected by the correction amount indicated by the correction amount data CAD.

[Problem that the invention seeks to solve]

By the way, when installing the Glojiekta 40, which can be used both as a stand-alone (Fig. 4) and a ceiling-mounted (Fig. 4), the position of the various maintenance knobs and buttons 41 should be taken into consideration. ,
Furthermore, in order to hide the surface 42 on which no makeup is applied, it is necessary to install the glossictor 40 upside down compared to when it is installed stationary.

With K in this way, if you want to obtain the same image on the screen 43 with a stationary installation and a ceiling-mounted installation, the stationary installation R (pM
At the same time, mark the arrow 5CA on the screen of the CRT in Figure 5.
In contrast to scanning from left to right and top to bottom as shown by NI, in the case of a ceiling-mounted installation, the scanning direction is reversed and from the right as shown by arrow 5CAN2 in Figure 5 ■. To the left
It must be scanned from bottom to top (based on top, bottom, left and right in case of stationary installation).

In Figure 5, the misconvergence f (expressed as an absolute value and shown in numbers without parentheses in the figure) without correction is 5 at an arbitrary position ELIJ in the upper left, and at an arbitrary position in the upper right. It is 2 at E'Rtr, 1 at the lower left position ELDVC which is point symmetrical to the upper right position ERU with the tube surface center 01 as the center, and 1 at the lower right position ELDVC which is point symmetrical to the upper left position ERU with the tube surface center O as the center. If the position ERD is 3, when using the Glossier in a stationary installation, the misconvergence amount is stored in the memory area corresponding to each position in the correction amount memory distribution in Figure 2 as shown by the number in parentheses in Figure 5. convergence N positive ft equal to
Make sure to remember the data.

If the Glodiector adjusted in this way is used as is for ceiling installation, the scanning direction will be opposite to that for stationary installation, and the data read address is determined by the elapsed time from the horizontal synchronization signal and vertical synchronization signal. The amount of correction appears vertically and horizontally symmetrically. Therefore, for example, the correction amount 5 for the upper left position ELU on the tube surface is the lower right position fi on the tube surface, as shown in FIG.
It appears as a correction amount of 5 at the ERDO location. As a result, the misconvergence amount 3 and the correction amount 5 do not match, and as shown in FIG.
The misconvergence amount 2 shown by the number in brackets in B) remains uncorrected.

The present invention has been made in consideration of the above points, and provides a convergence correction circuit for a projector with a simple configuration that prevents such misconvergence from remaining even when the installation of the projector is changed between stationary and ceiling-mounted. This is what I am trying to do.

[Means for solving problems]

In order to achieve such an object, the convergence correction circuit for a projector of the present invention includes a correction amount memory that stores data corresponding to the convergence correction amount on the tube surface of the pole ray tube, and a correction amount memory that stores data corresponding to the convergence correction amount on the tube surface of the pole ray tube. The read address signal H and VADk are generated sequentially, and the control signal C indicates whether the projector is installed on a stand-alone basis or on a ceiling.
0NT, an address generation circuit wr50 is provided for reversing the generation order of the read address signals HAD and VAD depending on whether the device is installed in a stationary position or installed on a ceiling.

[Effect]

The correction amount memo I720 stores convergence correction amount data CAD for each position on the CRT tube surface, and reads the read address signal HAD arriving from between the address generation circuits.
, convergence correction amount data CA corresponding to VAD
Dk bladder comes out. The digital-to-analog conversion circuit n converts the convergence correction amount data into CAD and an analog signal, and supplies the data to the convergence coil to correct the amount of misconvergence.

The address generation circuit culprit gradually increases the contents of the address signals HAD and VAD in the case of a stationary installation, and the address signal HAD in the case of a ceiling-mounted installation.

The content of VAD is gradually reduced. As a result, even if the scanning direction is reversed between the stationary installation and the ceiling-mounted installation, the read address signal I (AD) from the correction amount memory is read.

Since the generation order of VAD is also reversed, the same convergence correction amount data CAD will be read out for the same position on the CRT screen regardless of the installation mode, and misconvergence will occur even if the installation mode is changed. do not have.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 1, in which parts corresponding to those in FIG. 2 are denoted by the same reference numerals. In FIG. 1, the configuration of the address generation circuit blade is different from the circuit in FIG. 2.

In address generation circuit ■, horizontal address generation circuit 5
1 has an up/down counter configuration, and upon receiving a stationary/ceiling switching control signal C0NT, performs an up-count operation when the content indicates stationary installation, and conversely performs a down-count operation indicating ceiling-mounted installation. The horizontal address generation circuit 31 receives the horizontal synchronization signal H8YNC as a load command signal and is loaded with start address data from the selector 52. When the switching control signal C0NT indicates stationary installation, the selector 52 selects the start address data H8AI (
For example, the horizontal address generation circuit 51V
In response to this, when the switching control signal C0NT indicates that the installation is ceiling-mounted, the start address data H3A2 (for example, the maximum value rFFJ) stored in the second horizontal start address storage circuit N is given to the horizontal address generation circuit 51. .

Therefore, in the case of a stationary installation, the horizontal address generation circuit 51 generates the first start address data H8A, 1 (1') via the selector 52 when the horizontal synchronization signal agyNc arrives.
-00J), and counts up each time it receives the clock signal CLK, and supplies the gradually increasing count to the correction amount memory as a horizontal address signal HAD.

On the other hand, in the case of ceiling-mounted installation, the horizontal address generation circuit 31 is loaded with the second start address data usA2 (IF'FJ) when the horizontal synchronization signal H8YNC arrives, and counts down every time it receives the clock signal CLK. The operation is performed, and the count contents, which gradually decrease, are applied to the correction amount memory as the horizontal address signal HAD.

The vertical address generation circuit 55 has an up/down counter configuration, and performs an up-count operation whenever the switching control signal C0NT indicates stationary installation, and conversely performs a down-count operation when it indicates ceiling-mounted installation.

Vertical address generation circuit 55 receives vertical synchronization signal VSYNC as a load command signal, and is loaded with start address data through selector 56 when vertical synchronization signal VSYNC arrives. The selector is the switching control signal C0N.
When T indicates stationary installation, the start address data V stored in the first vertical start address storage circuit 57
Select SAI (for example, minimum value 1: OOJ)k, and select start address data VSA2 (for example, maximum value rFFJ) stored between the second vertical start address storage circuits when the switching control signal C0NT indicates the ceiling installation flu. and gives it to the vertical address generation circuit I.

The vertical address generation circuit amount is also the horizontal synchronization signal H8YN.
C as a clock signal. Therefore, when the vertical address generation circuit is installed stationary, the vertical synchronization signal VSYNC is
When the first start address data VSAI (rooJ) arrives, the first start address data VSAI (rooJ) is loaded via the selector, and every time the horizontal synchronization signal H8YNC is received, an up-count operation is performed, and the gradually increasing count content is used as the vertical address signal VAD to calculate the correction amount. to the memory 20.

On the other hand, in a ceiling-mounted Totogi, the vertical address generation circuit is loaded with the second start address data vsA2 (rFFJ) when the vertical synchronization signal VSYNC arrives, and is downloaded every time the horizontal synchronization signal I (SYNC) is received. The count contents, which are gradually decreased through a counting operation, are applied to the correction amount memory IJ 20 as a vertical address signal VAD.

In the circuit shown in Fig. 1, in the case of a stationary installation, the read operation is shifted from the memory area with a small address ("0000J") to the memory area with a large address ("FFFFJ)" in synchronization with image scanning. In the case of a ceiling-mounted installation, the read operation moves from the large address FFFFJ memory area to the small ``0000'' memory area.

In this way, by reversing the reading direction of the convergence correction amount data CAD from the correction amount memory in accordance with the scanning direction being the same in the case of a stationary installation and a ceiling-mounted installation, it is possible to install an arbitrary position on the tube surface. Even if the values are reversed, the same convergence correction is performed for the same position.

According to the circuit shown in FIG. 1, by controlling the readout address without changing the stored contents of the correction amount memo 1720, it is possible to respond to changes in the installation mode between the stationary and ceiling-mounted systems.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a convergence correction circuit for a projector with a simple configuration that can correct misconvergence so that it does not occur even when the installation of the projector is changed between stationary and ceiling-mounted. I can do it.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the convergence correction circuit for a projector according to the present invention, FIG. 2 is a block diagram showing a conventional circuit, FIG. 3 is a route map showing addresses of the correction amount memory, and FIG. 4 5 is a route map showing two installation modes of the projector, and FIG. 5 is a route map for explaining that the image position on the main surface of the CRT tube is reversed vertically and horizontally depending on the installation mode. Addition...Correction amount memory, n...Digital-to-analog conversion circuit, Cabinet...Address generation circuit, C0NT...
Stationary-ceiling switching control signal.

Claims (1)

[Claims] A correction amount memory stores data corresponding to the convergence correction amount on the tube surface of the cathode ray tube, and a read address signal for the correction amount memory is sequentially generated in accordance with the scanning of the electron beam, and the projector can be installed on a stationary basis or hung on a ceiling. A convergence correction circuit for a projector, comprising an address generation circuit that reverses the generation order of the readout address signals when the projector is installed in a stationary position and when installed on a ceiling, based on a control signal indicating installation.