JPS6194253A - Program searching controller - Google Patents

Abstract

PURPOSE:To avoid a case where the fluctuation of the tape speed causes a malfunction by monitoring directly the duty of a reproduction control signal through a high-speed microcomputer and by executing the monitoring with a microcomputer. CONSTITUTION:The functions of a duty discriminating means 2 and a cycle discriminating means 3 are attained by a program searching CPU10. The duty of a reproduction control signal can be measured directly through retrieval of program searching by means of a microcomputer since the CPU has a high- speed operation. In this case, the clock cycle is set at 1mus and the level is monitored every 20mus in the duty measurement mode of the reproduction control signal. No problem is produced even in case the cycle of the normal control signal is set at 25Hz or 30Hz since the duty of the control signal is measured directly. A countermeasure is also possible to the fluctuation of the tape speed since the level is checked at a high speed. Furthermore the tape speed is slowed down automatically with discrimination of the control cycle even in case the tape speed is increased too much. This produces no malfunction of retrieval.

Description

DETAILED DESCRIPTION OF THE INVENTION B) Industrial Application Field The present invention is a cueing control circuit for controlling cueing operations in a video tape recorder (VTR) J.

(b) Conventional technology In a helical scan VTR, a control signal of a constant frequency is normally recorded in the longitudinal direction of the tape by saturation recording, and is used for tracking during playback, etc. Furthermore, as the length of time available for frame drawing has increased, an automatic cue function has become necessary even in home VTRs.

Therefore, one method of cueing the VTR is to change the duty of the control signal at the start of the bone picture and record it. This method is used in β-type VTRs.

In other words, the duty of the control signal, which is normally a square wave with a duty of 50%, is changed for a certain period of time from 20% (R period) to 80% (L period) at the point where cueing is desired.
Change the duty to that and record it. Since the VTR's servo system is based on the rising edge of the control signal,
The servo is not disturbed by the timing variation of falling 5 (n→L).

When performing automatic cueing during playback, the VTIL is set to fast forward and rewind states while the control signal is being played back. Then, a change in the duty of the reproduction control signal is detected and the VTR is changed to the reproduction mode.

As the duty change detection means, JP-A No. 59-1
As shown in No. 17747, there is a method that basically uses an integrating circuit and performs discrimination based on a difference in output voltage corresponding to a change in duty of a reproduced co-roll signal. The disadvantage of this duty change detection means using an integrating circuit is that the tape speed changes greatly during fast forwarding or rewinding,
This is because errors in cue determination are likely to occur when the tape speed fluctuates rapidly.

Regarding the cue function of VTR, furthermore, Japanese Patent Application Laid-open No. 57-1
Mr. H Tail shown in 52381c, during playback of the VTR, write a cue control signal at any location (with a duty of 20%-80%), or conversely erase the written cue control signal. , a function that returns the duty to 50% can be considered. However, the above-mentioned publication discloses a device using a monomulti, and the configuration is complicated.

(c) Problems to be Solved by the Invention As stated above, the conventional duty change detection means essentially uses an integrating circuit, so there is a risk of malfunctions if the tape speed is unstable. Ta. Further, the configuration for realizing the above-mentioned cue writing and erasing functions is complicated.

The present invention has been made in view of this point.

An object of the present invention is to provide a cueing control device with no fear of malfunction.

B) Means for Solving the Problems In the present invention, a microcomputer performs duty change detection for cueing. That is, the duty of the N raw control signal is directly monitored to detect a change in duty. At the same time, a microcomputer is used as a means for detecting that the period of the reproduction control signal has become less than a predetermined value, thereby reducing the tape running speed.

B) Since the duty of the playback control signal is directly monitored and this monitoring is performed by a high-speed microcomputer, fluctuations in tape speed #i will not cause malfunctions. Furthermore, when the tape speed becomes too fast and the playback control cycle becomes less than a predetermined value, the tape speed is reduced, so that malfunctions do not occur.

(F) EXAMPLES The present invention will be described in detail below with reference to the drawings. FIG. 1 is a functional block diagram of the apparatus of the present invention, FIGS. 2 and 6 are circuit block diagrams of embodiments, and FIG. 4 is a flow chart showing the general operation of the cueing microcomputer (cuing CPU).

In FIG. 1, (1) is an input terminal for a reproduction control signal, (2) is a duty determination means for a reproduction control signal, and (3) is a period determination means for a reproduction control signal. Discrimination means (3)
The function of □ is realized by the cueing CPU.

(4) is a means for setting V
6] is the duty determining means (2) in response to the output of the VTR.
(7) is a period determining means (3).
This is a means for reducing the running speed of the tape in response to the direction in which the tape comes out.

Although Figure 1 shows the VTR as a separate block,
Actually, the cue control device of the present invention exists as a part of the system control circuit built into the VTR.

FIG. 2 shows a main microcomputer (main CPU) (101, starting LCP) that controls the operation of V'TR.
U@ and reel motor drive circuit ■ are shown.

In the VTR to which the present invention is applied, in fast forward and rewind modes, the tape is run at high speed by driving a reel stand. The two reel stands are rotated by one reel motor that drives an idler placed at an intermediate position. Since the idler mechanism is employed, only the take-up reel stand is driven in the fast forward mode, and only the supply reel stand is driven in the rewind mode.

In a configuration in which fast forwarding 9 and rewinding are performed by driving the reel stand, the reel motor (31) is normally controlled to have a constant rotational speed, so that the reel motor (31) is normally controlled to have a constant rotational speed, so that the reel speed changes as the tape winding diameter of the driven reel changes. , the tape running speed changes significantly. At the same time, the frequency of the playback control signal is also 25H.
(At normal playback speed, the frequency of the playback control signal is PAL/8EO.
25. in AM mode. ”b 30Hz in NT80 system.

). This frequency change is the cause of malfunctions in the conventional technology (which includes an integrating circuit).

Main OP U (lQi creates a signal to control the mode of the VTR according to the designation of the VTR mode designation means such as an operation switch. This control signal is supplied to the servo circuit, etc., and the mode of the VTR is controlled. .Furthermore, the main CPU (lα also creates a control signal for the cue 0PII (J).Furthermore, it creates a control signal for the head of the reel motor C3υ drive circuit.

The signals for cueing CPU mowing control include the REO signal (1
0a), Mu P81 signal (10b), Mu P81 signal (10
e) is used. The REC signal (10a) is a control signal for setting the VTR to recording mode. Ar11. AP8
1 signals (10b) (10C) are control signals that control the operation mode of the cueing CPU (20+), and the above six signals (10a) (10b) (10(+))
The below-described behavior of υ is specified. P of main CPUαα
IAOK input is PIAOj from cueing CPU (a)
It inputs the L signal (20B), and if there is an input indicating that the head portion has been detected, the main OPυα0) outputs a control signal to set the VTR in playback mode.

The signals used by the main CPU αOj to control the reel motor drive circuit ■ include the MR-H signal 4H10d, which is at R level in fast forward mode and rewind mode, and in other modes (for example, normal playback, slow mode, etc.) , control signal l specifying the reel motor rotation speed, reel motor C
F/round signal that specifies the rotation direction of 11l (10ei)
There is. In addition, the main CPU (IQI is 11.MO84
Q4Ci is used.

Cue CPLI, (TMP42Ci4QP) is 0 as mentioned above.
3-M) Control signal! The operation is controlled by (10 &) (10b) (100). The input (CTL IN) is a control signal input. As shown in Figure 4, the cueing CPU (a) operates in sequential search mode, normal index mode,
It has a head input mode and a head erase mode. Each control signal (101 (10b) (10 (+) state and cue C
The relationship with the mode of PU■ is as shown in FIG.

The VTR is not in recording mode ((REO signal is L),
P 81 , A P 8 I signal power ICH0flt
The first search mode is selected. In this mode, the duty of the playback control signal input to the control signal input (OTL IN) is directly monitored, and when the duty is 50% (Fig. 6 (a)), the PIACK output remains H and is set to 20%. -80% (Fig. 6(b)
) Outputs L. At the same time, the period of the reproduction control signal is also monitored, and the period is set to a predetermined value, for example, 400 μs.
If the following occurs, the speed will be reduced (8 PEED).
DN) Let the output be HV < .

Normal index mode uses RECt signal and APal
It is selected only when the signal is at R level. In this case,
The RECOTL signal (R, OTL signal) is output, and the index change (IND) signal becomes R level. R
, OTL signal is the control signal input (CTL IN
) is a signal that is at the R level for a period of 20% to 70% of the control signal period from the rising edge of the control signal (Fig. 7(a)) input to the control signal (Fig. 7(a)).
Figure 7 (see cut).

REC credit g Ka L V w Te A P 81 %A P 8
1 In the case of a combination of signal high and H, the cueing CPU
Kari is in head-hitting mode. In this mode, in addition to the engineering ND signal being at R level, the WRITE C! TL(W
, QTL) signal, and a playback mute signal (PB0MUTE signal) are output. The timing of the W, OTL signal and the FB, MUTE signal with respect to the reproduction control signal (input to the control signal input) is shown in FIG. W, OTL signal (Figure 8(b)) is the playback control signal (L, <(a)) f) rising 4C ML-C2
This is a signal at D96-6096KH level. Also, as shown in (C), the i' B and M TJ T B signals are 5%-18 in synchronization with the rising edge of the reproduction control signal.
0% is a signal for level # failure.

When the REO signal is at L level, AF81. P81 signal is i
In the case of combination ze of t and L! When the jc company distribution amount becomes 7, the IND @ issue becomes Hv level. Easy to see [, u@1ie in apical removal 4-F) PR, M'U'T, Ett and lB
゛S AE CTL (E, C'l"L) gr4J-$ output 1
It will be done.

E, CTL Signal Co., Ltd. 9th WA, like the playback controller #
10% -50 in synchronization with the start-up signal.
%0... This is a signal that becomes a level.

3 of the above head entry, deletion, and normal index
(Mo)' Cancer, 剋, arL, w.

CI'L, E, C'T: L signal 4j level timing company.

Input to 2nd+roll signal input (OTL IN)
Set based on the period of the large control signal.

Namely. Each signal is created based on the data I of the previous cycle. This allows PAL/810mm (25
It can also automatically support two systems: nz) and NT80 (30H2) 17).

Misfortune, in the 5th @ h, IIi, with the state marked as inoperable,
1laiLOPUmt! , q*, )-shaped 11f6D-lower IACK output is set to H level, and other outputs are set to L level.

In Figure 2, the drive circuit for the reel motor (2) is the reel motor rotation direction switching circuit (2), the fast forward and rewind drive circuits that drive the reel motor (to), and the fast forward and rewind drive circuits that drive the reel motor (to). Fast forward 9, slow speed except when rewinding 2 # 毫 - evening (
2) is provided with a speed reduction circuit for reducing the rotational speed of the reel motor C1υ during fast forwarding 11 and rewinding.

Reel motor drive circuit c (IIIi mainly main CP
Controlled by Miss U. Depending on the level of the F/T signal (10@), the state of the rotation direction switching circuit ■ changes, the direction of the current flowing through the reel motor changes, and the rotation direction of the reel motor, which is the ll[R motor, is corrected (forward). Change direction and reverse direction. When the reel stand is driven at low speed, such as during normal playback or slow playback, a corresponding reference voltage is created in the reference voltage creation circuit in response to a control signal from the company's main ct'u@. A voltage substantially the same as this reference voltage is generated at the emitter of the first transistor (Ql),
It is supplied to the rotation direction switching circuit (2) via the diode (D). Therefore, constant voltages corresponding to a plurality of modes are applied to the reel motor (2).

M if the VTR is set to fast forward or rewind mode
The R-11 signal (10d) becomes R level.

As a result, the second transistor (Q2) is turned on, the third transistor (Q3) is also turned on, and the power supply voltage (
A voltage equal to 1B) is applied to the reel motor clI, and the reel motor G11l rotates at high speed. At this time,
Since the 8PEED DN signal is at L level, the transistor (Q4) is in the on state and the resistor (
Both ends of R1) are shorted and the N flow of the PNP) transistor (Q3) is almost unrestricted. On the other hand, 8
When the PEEDDN output becomes R level, an L level signal is applied to the pace of the fourth transistor (Q4) due to the operation of the inverter (support), so it is turned off, and the emitter of the second transistor (Q2) and ground. A resistor (R1) is inserted between them, and the current flowing through the PNP transistor (Q3) is 1
! 1@ will be done. Therefore, the rotation speed of the reel motor (2) decreases.

Figure 3 shows the top of the CPU ■ OTL head related to output.
It shows the recording/reproducing control circuit, etc. The recording and reproducing control circuit (Inc.) is composed of a bridge circuit made up of transistors connected to both ends of the CTL head frame, and transistors controlling each of the transistors (Q5') to (Q6) of this prefuji circuit.

First, the operation during normal recording and reproduction will be explained. During recording, the REO signal (reverse) goes to H level, the fifth transistor (Q5) is turned on, and the twelfth transistor (Ql2) is in a state where it can be turned on. A 3 Q Hz square wave, which is the control signal to be recorded, is the first signal across the block.
1 transistor (Qll). This 5 Q Hz signal is created from the vertical synchronization signal of the video signal to be recorded. 11th transistor (Qll)
When the base level of , the 11th transistor (Qu)
, the seventh transistor (Q7), and the fifth transistor (Q'
, 5) are on, the 12th transistor (Q[), the 8th transistor (Qs), the 6th transistor (Qs)
is off, so C! A current of arrow A flows to TL and to C.

On the other hand, when the base of the 11th transistor (Qll) is at L level, the 12th transistor (Qtz), 1st 8th transistor (Qll), 3g6) fungistor (Qs) turns on and becomes 1, and the 11th transistor (Qll) ), F7)
The transistor (Q7) is turned off. Therefore, current flows through the CjTL head in the direction of arrow B.

The fifth transistor (Qs) is also on, but since there is a resistor (1), current mainly flows in the direction of arrow B.

At this time, since the FB0MUT5 signal - is at the L level, the selector switch selects the L side, and the collector of the fifth transistor (Qs) is connected to the input of the CTL amplifier (9). Although the fifth transistor (Qs) is in the on state, it has a small on-resistance, so the collector voltage changes depending on the change in the direction A and the direction B. , this voltage is applied to the amplifier (5υ, including the phase comparison circuit J & etc. of the servo circuit I path C cap 1 stator through Schmidt@Roguchi)
(to) □ and ′, end as control signal, child c
C'T'LOUT') (a, output, output., During playback, R1, C; signal (I21 is L level -; l1
1), the sixth transistor (Qs) is turned off, the seventh transistor (9th transistor) and the fifth transistor (Qs) are also turned off, and the power to the eighth transistor CQ f ) is turned on. Therefore, the current change generated in the CTL head due to reproduction is amplified by the amplifier, and waveform-shaped by a Schmidt circuit sieve to obtain a square wave reproduction control signal. This reproduction control signal is also applied to the servo circuit ω and the terminal -.

1) with the high pass filter (IIPN')! Since the MP-R1 signal is 11V and a bell except during fast forwarding and rewinding, HPF541 is the 14th transistor (Q14).
is grounded to ground unnecessary high frequency components.

On the other hand, when the VTR is set to fast forward or rewind mode, the MR
The -R1 signal (equipment) goes to L level, and the 14th transistor (Q14) also turns off. Therefore, by running the tape at high speed without attenuating high frequency components, sufficient amplification and shaping can be performed even if the frequency of the reproduction control signal becomes high.

When the cueing CPU ■ is in the normal indexing mode, the R1CTL signal (in FIG. 7) ) □□□ is applied to the base of the tenth transistor (QIO). R,OT
During the period when the L signal is at R level, the 10th transistor (Q
Even if the control signal (IO) is turned on and the control signal (to) is at H level, the eleventh transistor (Qll) is turned off and a current flows through the OTL head in the direction of arrow B.

In other words, the control signal (to) of the output of the block
A current flows in the input direction for a period of 20% of the control signal period from the rising edge of the signal. Then, the current flows in the B direction for 80% of the period thereafter. As a result, it is the same as applying a control signal of 20%''-8096L to the base of the 11th transistor (Qll).

In the head-shot mode, W, CTL signal (5 (Fig. 8(b)) tLL123 )9 xi (Qt
3) The FB and MUTE signals (a (Fig. 8 (C)) are supplied to the O base as control signals to the selector switch Co., Ltd. The PB and MUTE signals are supplied to the OTL OUT terminal (4
When the playback control signal (Fig. 8(a)) generated at 9i rises, the selector switch ω selects the L side, and
The rising edge of the reproduction control signal is always applied to the OTL OυT terminal - via the amplifier 6D or the like. W.

When the OTL signal (Fig. 8(b)) becomes H level, the 13th
The transistor (Q13) is turned on, and the sixth transistor (Qs) is turned on. At this time, since it is in the reproducing state, the eighth transistor (Qs) is turned on, and a current in the direction of arrow B flows through the OTL head α. At this time, FB
, the MUTE signal is at level ■, so the fifth transistor (Q
The collector of s) is grounded. Therefore, the current flowing through the resistor (R2) does not affect the amplifier (5D, Schmitt circuit Q).

Since the current in the direction of arrow B corresponds to when the block-output control signal is at L level as described above, the portion normally recorded with the current in the incoming direction is rerecorded with the current in the B direction. That is, the control signal shown in FIG. 6(b) is recorded. When the W and OTL signals go to L level, the 13th
Although the transistor (Q13) is turned off, the sixth transistor (Q6) is not cut off until the terminal voltage of the capacitor (C) reaches a predetermined value. That is, the current in the direction of arrow B, which corresponds to the H level of the W and OTL signals, gradually decreases, and the fall is smooth instead of abrupt as shown in FIG. 8(b).

The IND signal (481) is at the H level in the initial injection mode, is applied to the Schmitt circuit, and operates to widen the width of its hysteresis.

This is to prevent the Schmitt circuit from malfunctioning due to abnormal operation of the recording/reproduction control circuit.

When erasing the head, the E and OTL signals (Fig. 9(b)) are
Applied to the pace of Tosangista (Q9), and furthermore, FB
1MUTE signal and IND signal are also applied in the same way as at the time of head input. In this case also FB.

The operation of the MLITE signal ensures that the rising edge of the reproduction control signal is applied to the cue OFυ@).

When the ninth transistor (Q9) is turned on during the H level period of the E and CTL signals, the seventh transistor (Q7) is turned on and the eighth transistor (Q8) is turned off. Therefore, a current in the direction of arrow A flows through the CTL head and is grounded via the changeover switch (3). The current in the direction of arrow A is the same as the current direction when the block output is at H level, so
20% (H) - 80% (L) control signal (6th
Even if the signal shown in Figure (b)) is recorded, it is rewritten to a signal with a duty of 50%.

Next, "The overall operation will be explained. When the VTR is set to the recording mode by the mode specifying means U,
The 0REC signal (10B) from U (11) is sent to RV hair A/
Toner F), capstan motor, and head motor start rotating. After a predetermined time delay from the rise of this REO signal (FIG. 10(a)), the main 0PtlQa AP81 signal goes to H level, and the cueing CPU (J is designated to normal index mode. 10th
The period when (b)) is at the R level is set to 8 seconds in βI mode and 12 seconds in βri mode.
The duty force of the control signal supplied and recorded is 120%-80%.

Set the sequential search mode to the main CPU using the mode specifying means aυ.
(When instructed to lQj, it operates as shown in chart 70 in Figure 11. From the main 0Ptl (IQI), the H level AP81.AP81 signal is activated, and the cueing CP
U■ is set to sequential search mode □. Furthermore, main 0Pt
l (IQI is set by setting the MR-H signal etc. to H level and
Set TR to fast forward or rewind mode.

Then, the tape is run until the PIAOK signal from the 3PU (lQi) reaches the L level. PIAON
When the signal goes to L level, after stopping the VTR,
Set to play state.

The cueing CPU ■ is designated to the sequential search mode and performs the sequential search process. The sequential search process is a process of determining the duty of the reproduction control signal as described above, and further determining the cycle. Therefore, the HM and L periods of the reproduction control (reproduction CTL) signal are counted and the respective count values are compared.

In this case, for example, the count value corresponding to the R period is doubled and compared with the count value for the L period. If the count value of the L period is larger, it may be determined that it is a 20%-80% duty portion, and if the opposite is the case, it may be determined that it is a 50% duty portion. At this time, the threshold value is 33.3%.

If it is determined that it is the 20%-80% duty part, the PI
Set the AOK signal to L level. When it is determined that it is a 50% duty portion, the PIACK signal is set to H level. Furthermore, in the next step, it is determined whether the sum of the count value of the H period and the count value of the L period (corresponding to the period of the reproduction control signal) is smaller than 400 μS. If it is small, the 8PEED DN signal is set to H level, and if it is large, it is set to L level.

8PEED When the DN signal reaches the 5th level during fast forwarding or rewinding mode, the fourth transistor (Q4) of the reel motor drive circuit turns off and the serial motor (3) J
The rotational speed of the tape decreases, and the tape speed also decreases. In forward search using a microcomputer, the duty of the reproduction control signal can be directly measured. This is because the CPU operates at high speed; in the embodiment, the clock cycle is 1 μs, and the level is monitored every 25 μs when measuring the duty of the reproduction control signal. Since the duty is directly measured, it can be used without any problem even if the normal control signal period is 25, 2 or 3 QHz. Since the level is checked at high speed, it can also respond to fluctuations in tape speed. Even if the tape speed suddenly increases, the tape speed is automatically reduced by determining the control cycle, so no search errors occur.

If it is desired to write an index signal at any location on the recorded tape, the VTR is set to playback mode and the head write switch is turned on at the desired screen. In response, the main 0Ptl(lQi) sets the AP81 signal to the R level (see the flowchart in FIG. 12).

Main OP tJ (AP81 signal from IQI is set to Ii level for 8 seconds (or 12 seconds). AP81
While only the signal is at H level, the cueing CPU (1) is in the cueing mode.

In the head input mode, first, the period T for measuring the period of the reproduction control signal is 31.33 m3 or more, 35 m3 or more.
．． If it is less than 33 m', it is determined that the cycle is normal, and in synchronization with the rising edge 9 of the next playback control signal, W,
Outputs OTL signal, FB, and MUTE signal. Also, IN
The D signal is at R level.

If the period is determined to be abnormal, the main (3PU(lQi)
If there is a mode change based on an instruction from , return to Figure 4 (■). , In addition to this, at the position where I instructed you to hit the head, fl
, If the reproduction control signal cycle is disturbed due to an error in the mode change of β-seed, etc., the output will be temporarily stopped, and the output will be restarted when the normal cycle (33, 33m! ±2m5) is reached. This prevents the cue signal from being recorded erroneously.

When the period of the playback control signal is within the normal range, the W, CTL signal, and PB signal are determined based on the measured period.
, sets each period of the MUTE signal. That is, since each period is set by always noticing the previous reproduction control cycle determination, either 25H2 or 3Q HZ control signals can be used.

When the beginning erasing mode is set by the mode specifying means, first the sequential search mode is activated and the portion where the beginning signal is recorded is searched. When the cue signal is detected, only the AP81 signal goes to R level), and the cue erase mode is entered. The head erase mode is almost the same as the head input mode.The difference is that the period during which the AP81 signal is at the H level is 20 seconds, and the output signal is the E instead of the W and CTL signals.
, C'l'L signals.

In addition, in the configuration of the embodiment, the playback control cycle is 400μ.
When the tape speed becomes smaller than s, the 8FEED DN signal is output, and when the tape speed decreases, the 5FEED DN signal is output again.
The DN signal returns to L level.

That is, the reel motor is configured to be braked every time the tape speed becomes greater than a predetermined value. As a result, the tape speed is reduced and controlled so as not to exceed a certain speed. On the other hand, each time the period of the reproduction control signal exceeds a predetermined value, the plurality of output states of the one-head OFυ change, and for example, the plurality of output lines sequentially become R level. Or, Pi≠Lee output changes),
Correspondingly, a method may also be considered in which the reel motor drive circuit applies a voltage corresponding to the cue CPU output to the reel motor, thereby reducing the tape speed.

Furthermore, there are multiple output states corresponding to the cycle of the playback control signal (for example, when the cycle is fl, the human output is at H level,
The cueing CPU has a state in which the B output becomes H level when the output is fl, and the voltage supplied to the reel motor changes in response to this output change, causing the tape speed to decrease. can also be considered.

(g) Effects of the Invention As described above, the present invention is effective because it prevents the cueing operation from malfunctioning due to fluctuations in the tape speed.

[Brief explanation of the drawing]

The drawings are all related to the present invention; FIG. 1 is a functional block diagram, FIGS. 2 and 6 are circuit block diagrams of the embodiment, FIG. 4 is a flow chart showing the operation of the cueing CPU, and FIG. Explanatory diagrams showing the relationship between the combination of control signals from the main CPU and the operation mode of the cueing CPU, FIGS. 6, 7, and 8
9 and 10 are waveform surfaces, FIG. 11 is a flowchart showing the operation in the head search mode, and FIG. 12 is a flowchart showing the operation in the head input mode. (1)......Playback control signal input terminal, (
2)...Duty determination means, (3)...
...Period determination means, (4)...Fast forward/rewind setting means, (5)...VTR1 (6)...
- Reproduction mode setting means, (7)... speed reduction means.

Claims (1)

[Claims] (1) means for setting a video tape recorder to a first mode in which the tape runs at high speed; means for reproducing a playback control signal in the first mode; and determining duty by inputting the playback control signal. duty determining means; cycle determining means for inputting the playback control signal and determining that the cycle is smaller than a predetermined value; and means for changing the mode of the video tape recorder based on the output of the duty determining means; A cueing control device comprising means for reducing the tape speed based on the output of the cycle determining means.