JPS6193646A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS6193646A JPS6193646A JP21461984A JP21461984A JPS6193646A JP S6193646 A JPS6193646 A JP S6193646A JP 21461984 A JP21461984 A JP 21461984A JP 21461984 A JP21461984 A JP 21461984A JP S6193646 A JPS6193646 A JP S6193646A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- pattern
- tensile stress
- manufacturing
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路に係り、特に、そのチップに
形成される配線のパターンに関す。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor integrated circuit, and particularly to a wiring pattern formed on a chip thereof.
半導体集積回路の高集積化が進むに伴い、半導体チップ
に形成される配線のパターンが細幅化してきている。2. Description of the Related Art As semiconductor integrated circuits become more highly integrated, wiring patterns formed on semiconductor chips are becoming narrower.
この配線パターンの細幅化は、半導体集積回路(LC)
の製造過程における該配線の断線発生と言う製造トラブ
ルに繋がる場合があり、該トラブルに対する対応策が求
められる。This thinning of the wiring pattern is the result of semiconductor integrated circuits (LC).
This may lead to manufacturing troubles such as disconnection of the wiring during the manufacturing process, and countermeasures are required to deal with these troubles.
第2図は半導体チップに形成される配線の従来の一例を
示した平面図である。FIG. 2 is a plan view showing an example of conventional wiring formed on a semiconductor chip.
同図において、la、lbはそれぞれ同一半導体チップ
に形成された例えばトランジスタ、2a、 2bはトラ
ンジスタlas lbのそれぞれから配線を導出するた
めのコンタクトホール、3は例えばアルミニウムなどの
導電体からなりコンタクトホール2a、2bを通してト
ランジスタ1aと1bとを接続する配線である。In the figure, la and lb are transistors formed on the same semiconductor chip, 2a and 2b are contact holes for leading wiring from transistors las and lb, respectively, and 3 is a contact hole made of a conductor such as aluminum. This is a wiring that connects transistors 1a and 1b through 2a and 2b.
配線3のパターンは、他のパターン多くは他の配線パタ
ーンに干渉されない限り直線状に形成されるのが一般で
ある。Generally, the pattern of the wiring 3 is formed in a straight line unless it is interfered with by other wiring patterns.
また、配線3のパターン幅は、ICの高集積化により例
えば2.0−1.5→1.0μmと細くなって来ている
。Furthermore, the pattern width of the wiring 3 has become narrower, for example, from 2.0-1.5 to 1.0 μm, due to higher integration of ICs.
一方、例えばアルミニウムの配線3をこのように直線状
で幅を細くした場合、後工程にある例えば熱処理工程な
どにおいて該配線3が断線する場合があることが見いだ
され、製造トラブルとじて問題になって来た。On the other hand, it has been found that when the wiring 3 made of, for example, aluminum is made straight and has a narrow width, the wiring 3 may break during a subsequent process such as a heat treatment process, which may cause problems in manufacturing. I came.
上記問題点は、他のパターンに干渉されることなく直線
的な帯状に形成可能な配線パターンが、引張応力を緩和
する非直線的な帯状に形成されてなる配線を有する本発
明の半導体集積回路によって解決される。The above problem is solved by the semiconductor integrated circuit of the present invention, which has a wiring pattern that can be formed into a linear band shape without being interfered with by other patterns, but is formed into a non-linear band shape that relieves tensile stress. solved by.
上記問題点である製造過程における配線の断線は、該配
線自体が内部応力を有し、該配線のパターンが直線的な
帯状であることから、後工程にある例えば熱処理工程な
どの際に増大する引張応力に抗しきれず粒界で破断する
ことに起因するものと考えられる。The above-mentioned problem of disconnection of wiring during the manufacturing process increases during post-processing, such as heat treatment, because the wiring itself has internal stress and the wiring pattern is in the form of a straight band. This is thought to be due to the failure to withstand tensile stress and fracture at grain boundaries.
従って、該パターンを引張応力を緩和する非直線的な帯
状例えばジグザグをなす帯状にすることにより、該後工
程の際に増大する引張応力を緩和することが出来て、該
配線の断線発生を防止することが可能になる。そしてこ
のようにするのは、問題となる配線のみを対象とすれば
よい。Therefore, by forming the pattern into a non-linear band shape that relieves tensile stress, such as a zigzag band shape, it is possible to alleviate the tensile stress that increases during the post-processing and prevent the occurrence of disconnection of the wiring. It becomes possible to do so. This can be done only for the wiring in question.
かくして、高集積化されても製造に際して配線の断線発
生を生じ難いICが提供出来て、該ICの製造トラブル
を低減させる。In this way, it is possible to provide an IC that is less likely to cause disconnection of wiring during manufacturing even if it is highly integrated, thereby reducing manufacturing troubles of the IC.
以下本発明の一実施例を図により説明する。企図を通じ
同一符号は同一対象物を示す。An embodiment of the present invention will be described below with reference to the drawings. The same reference numerals refer to the same objects throughout the design.
第1図は半導体チップに形成される配線の本発明による
一実施例を示した平6面図で、第2図に対応する図であ
る。FIG. 1 is a hexagonal plan view showing one embodiment of the present invention of wiring formed on a semiconductor chip, and corresponds to FIG. 2.
第1図図示の配線3aは、第2図図示の配線3を置換し
たもの゛で、そのパターンはコの字を組み合わせたジグ
ザグをなす帯状になっている。The wiring 3a shown in FIG. 1 is a replacement for the wiring 3 shown in FIG. 2, and its pattern is a zigzag strip formed by combining U-shapes.
具体的には、配線3aの材料がアルミニウムの場合、そ
の寸法a、bSc、dおよび厚さは、例えば、それぞれ
約1.5μm、約3.0μm1約1.5μm、約10c
rm、約1.0.czmである。Specifically, when the material of the wiring 3a is aluminum, its dimensions a, bSc, d and thickness are, for example, approximately 1.5 μm, approximately 3.0 μm, approximately 1.5 μm, and approximately 10 μm, respectively.
rm, about 1.0. It is czm.
この配線3aは、帯状の中心線において、配線3aの長
手方向に対して略直角な方向の部分を有するため該長手
方向に伸縮可能である。このことから、製造過程におい
て引張応力が掛かっても従来のように破断することが無
く、製造トラブル発注を抑制出来る。This wiring 3a has a portion in a direction substantially perpendicular to the longitudinal direction of the wiring 3a in the center line of the strip, and therefore can be expanded and contracted in the longitudinal direction. For this reason, even if tensile stress is applied during the manufacturing process, it will not break like in the past, and orders for manufacturing problems can be suppressed.
なお、上記実施例における配線3aのパターンは、コの
字を組み合わせたジグザグをなす帯状であるが、本発明
は、その原理からして、この形状に限定されるものでは
無く、例えば、■の字を組み合わせたジグザグをなす帯
状であってもよく、また、これらのジグザグは部分的に
設けられていてもよい。In addition, although the pattern of the wiring 3a in the above embodiment is a zigzag strip formed by combining U-shapes, the present invention is not limited to this shape in view of its principle. It may be in the form of a band with zigzags formed by combining letters, or these zigzags may be provided partially.
〔1発明の効果〕
以上説明したように、本発明の構成によれば、高集積化
されても製造に際して配線の断線発生を生じ難いICが
提供出来て、該rcの製造トラブル低減を可能にさせる
効果がある。[1 Effect of the Invention] As explained above, according to the configuration of the present invention, it is possible to provide an IC that is unlikely to cause disconnection of wiring during manufacturing even if it is highly integrated, making it possible to reduce manufacturing troubles of the RC. It has the effect of
図面において、
第1図は半導体チップに形成される配線の本発明による
一実施例を示した平面図、
第2図は半導体チップに形成される配線の従来の一例を
示した平面図である。
また、図中において、
1aSlbはトランジスタ、
2a、2bはコンタクトホール・
3.3aは配線、
a、bScSdは寸法、
をそれぞれ示す。In the drawings, FIG. 1 is a plan view showing an example of wiring formed on a semiconductor chip according to the present invention, and FIG. 2 is a plan view showing an example of a conventional wiring formed on a semiconductor chip. In the figure, 1aSlb is a transistor, 2a and 2b are contact holes, 3.3a is wiring, and a and bScSd are dimensions, respectively.
Claims (1)
成可能な配線パターンが、引張応力を緩和する非直線的
な帯状に形成されてなる配線を有することを特徴とする
半導体集積回路。A semiconductor integrated circuit characterized in that a wiring pattern that can be formed into a linear band shape without being interfered with by other patterns has wiring formed in a non-linear band shape that relieves tensile stress.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21461984A JPS6193646A (en) | 1984-10-13 | 1984-10-13 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21461984A JPS6193646A (en) | 1984-10-13 | 1984-10-13 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6193646A true JPS6193646A (en) | 1986-05-12 |
Family
ID=16658723
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21461984A Pending JPS6193646A (en) | 1984-10-13 | 1984-10-13 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6193646A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62185072U (en) * | 1986-05-15 | 1987-11-25 | ||
WO1997040528A1 (en) * | 1996-04-19 | 1997-10-30 | Matsushita Electronics Corporation | Semiconductor device |
-
1984
- 1984-10-13 JP JP21461984A patent/JPS6193646A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62185072U (en) * | 1986-05-15 | 1987-11-25 | ||
JPH0517269Y2 (en) * | 1986-05-15 | 1993-05-10 | ||
WO1997040528A1 (en) * | 1996-04-19 | 1997-10-30 | Matsushita Electronics Corporation | Semiconductor device |
EP0834913A1 (en) * | 1996-04-19 | 1998-04-08 | Matsushita Electronics Corporation | Semiconductor device |
US6081036A (en) * | 1996-04-19 | 2000-06-27 | Matsushita Electronics Corp. | Semiconductor device |
EP0834913A4 (en) * | 1996-04-19 | 2001-09-05 | Matsushita Electronics Corp | Semiconductor device |
KR100299338B1 (en) * | 1996-04-19 | 2001-10-19 | 마츠시타 덴끼 산교 가부시키가이샤 | Semiconductor device |
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