JPS6193100U - - Google Patents

Info

Publication number
JPS6193100U
JPS6193100U JP17751984U JP17751984U JPS6193100U JP S6193100 U JPS6193100 U JP S6193100U JP 17751984 U JP17751984 U JP 17751984U JP 17751984 U JP17751984 U JP 17751984U JP S6193100 U JPS6193100 U JP S6193100U
Authority
JP
Japan
Prior art keywords
output
signal
level control
control circuit
stereo input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17751984U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17751984U priority Critical patent/JPS6193100U/ja
Publication of JPS6193100U publication Critical patent/JPS6193100U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の構成図、第2図、第3図、第4
図はそれぞれ本考案の実施例を示す図である。 1…バツフアーアンプ、2…減算回路、3…遅
延回路、4…増幅回路、5…レベルコントローラ
ー、6…加算回路。
Figure 1 is a conventional configuration diagram, Figures 2, 3, and 4.
Each figure shows an embodiment of the present invention. 1...Buffer amplifier, 2...Subtraction circuit, 3...Delay circuit, 4...Amplification circuit, 5...Level controller, 6...Addition circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ステレオ入力信号より、その差信号成分を取り
出す減算回路と、その出力信号を任意の遅延時間
をもつて遅延する遅延回路と、その出力信号を、
増幅もしくは減衰させるためのレベルコントロー
ル回路とを備え、前記レベルコントロール回路の
出力を前記ステレオ入力信号に各々加算して出力
とすることを特徴とする音響付加装置。
A subtraction circuit extracts the difference signal component from the stereo input signal, a delay circuit delays the output signal with an arbitrary delay time, and the output signal is
1. A sound adding device comprising: a level control circuit for amplifying or attenuating; the output of the level control circuit being added to the stereo input signal to produce an output.
JP17751984U 1984-11-22 1984-11-22 Pending JPS6193100U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17751984U JPS6193100U (en) 1984-11-22 1984-11-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17751984U JPS6193100U (en) 1984-11-22 1984-11-22

Publications (1)

Publication Number Publication Date
JPS6193100U true JPS6193100U (en) 1986-06-16

Family

ID=30735086

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17751984U Pending JPS6193100U (en) 1984-11-22 1984-11-22

Country Status (1)

Country Link
JP (1) JPS6193100U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010529780A (en) * 2007-06-08 2010-08-26 ドルビー・ラボラトリーズ・ライセンシング・コーポレーション Hybrid derivation of surround sound audio channels by controllably combining ambience signal components and matrix decoded signal components

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4948962A (en) * 1972-06-14 1974-05-11
JPS49110301A (en) * 1973-02-20 1974-10-21

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4948962A (en) * 1972-06-14 1974-05-11
JPS49110301A (en) * 1973-02-20 1974-10-21

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010529780A (en) * 2007-06-08 2010-08-26 ドルビー・ラボラトリーズ・ライセンシング・コーポレーション Hybrid derivation of surround sound audio channels by controllably combining ambience signal components and matrix decoded signal components

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