JPS618984B2 - - Google Patents

Info

Publication number
JPS618984B2
JPS618984B2 JP56172252A JP17225281A JPS618984B2 JP S618984 B2 JPS618984 B2 JP S618984B2 JP 56172252 A JP56172252 A JP 56172252A JP 17225281 A JP17225281 A JP 17225281A JP S618984 B2 JPS618984 B2 JP S618984B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56172252A
Other languages
Japanese (ja)
Other versions
JPS5875230A (ja
Inventor
Hidenori Taniguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP56172252A priority Critical patent/JPS5875230A/ja
Publication of JPS5875230A publication Critical patent/JPS5875230A/ja
Publication of JPS618984B2 publication Critical patent/JPS618984B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
JP56172252A 1981-10-28 1981-10-28 入出力制御回路 Granted JPS5875230A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56172252A JPS5875230A (ja) 1981-10-28 1981-10-28 入出力制御回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56172252A JPS5875230A (ja) 1981-10-28 1981-10-28 入出力制御回路

Publications (2)

Publication Number Publication Date
JPS5875230A JPS5875230A (ja) 1983-05-06
JPS618984B2 true JPS618984B2 (show.php) 1986-03-19

Family

ID=15938439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56172252A Granted JPS5875230A (ja) 1981-10-28 1981-10-28 入出力制御回路

Country Status (1)

Country Link
JP (1) JPS5875230A (show.php)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021145642A (ja) 2020-03-23 2021-09-27 株式会社リコー 担体及び検査方法

Also Published As

Publication number Publication date
JPS5875230A (ja) 1983-05-06

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