JPS6188376A - Reading circuit - Google Patents

Abstract

PURPOSE:To detect an abnormal condition due to a noise, etc., as an error and to improve reliability with a simple composition by installing a circuit which compares and collates an output signal of the first and third FF. CONSTITUTION:A reading signal A is fetched by the first clock B at the first FF7 of a data reading circuit, and reset by the second clock C after the data are recognized. The second FF8 is set by the signal A and reset by a timing signal D after the data are recognized. An output G of the FF8 is added to the third FF9, set by the third clock E and reset by the clock C. An output F of the FF7 is added to AND gates 10 and 13 and an output F' is added to an AND gate 11. An output H' of FF9 is added to gates 10 and 11 and an output H' is added to the gate 13. When a check timing K occurs, the output signal of FFs 7 and 9 is compared and collated at the gates 10, 11 and 13 and an OR gate 12, and the abnormal condition due to a noise, etc., is detected.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention involves reading information recorded in the form of perforations or marks on a recording medium such as a card or sheet twice and collating the obtained information. malfunction.

This invention relates to a reading circuit for testing.

[Background of the invention]

In order to increase the reliability of reading information on recording media such as cards and sheets, one reading unit reads the same information twice at a later time, compares and cross-checks the obtained information, and performs the reading operation. A double-read verification circuit is used to check whether the reading was successful. However, in all conventional reading circuits, the information reading signal on the medium must be above a certain value. This has the disadvantage that when the read signal falls below a certain value due to deterioration of the read element or changes in the amplifier, information continues to be dropped.

FIG. 1 shows a conventional reading circuit, and FIG.

This shows the time chart.

The first flip-flop 1 is set by seeing the read signal A with the tal clock B which is generated synchronously with respect to the read I/C, and the second flip-flop is set by seeing the read signal A with the second clock E. Set 2. When the output F of the first flip-flop l and the output H of the second flip-flop 2 are both true at the check timing that occurs after the second clock E, -F'-
The output F of the first flip-flop l and the second
When the outputs H of the flip-flops 2 are both false, the condition of the AND gate 3 cannot be satisfied and the data J is read as no data (timing of the second data in FIG. 2). In other words, it is recognized that it has been read normally. The first flip-flop!
When the output F of the output F and the output H of the second flip-flop 2 are false, the condition of AND gate 4 or AND gate 6 is met, so it is recognized that the error (ER) has been read abnormally through OR gate 5. do. However, Fig. 2
If the read signal A falls before the first clock B due to some factor such as data timing, the first
flip-flop 1 and second flip-flop 2
are not set, output F and output H both become false, and it is recognized that data J has been read successfully without data J, resulting in information being omitted.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a reading circuit that detects an error when the read signal falls before the first clock signal is generated, instead of causing the read signal to fail.

[Summary of the invention]

The present invention is characterized in that, in a reading circuit for data recognition in a card reading device, a first flip-flop receives a read signal using a first clock and is reset after recognizing the data; A second flip-flop is set and reset after recognizing data, and a second clock generated later than the first clock captures the output signal of the second flip-flop.

The third flip-flop is reset after recognizing data, and a path for comparing and matching the output signals of the first flip-flop and the third flip-flop is provided.

[Embodiments of the invention]

An embodiment of the present invention will be described below.

Referring to FIGS. 3 and 4, the second flip-flop 8 is set by the read signal A and reset after the check clock.

The read signal A is seen by the first clock B, which occurs synchronously with respect to the read, and the first ! At the second clock E, the third flip-flop 9 is set by looking at the output G of the @2 7-lip flop 8 which is sent by the read signal A. At the check timing that occurs after the second clock E, the first flip-flop 1
When the output F of and the output H of the third flip-flop 9 are both true, the data J is read as data present through the AND gate 10 (timing of the first data in FIG. 4), and the first flip-flop 7 When the output F of the third flip-flop 9 and the output H of the third flip-flop 9 are both false, the AND gate 100 condition cannot be satisfied and the data J is read as no data. (Timing of the second data in FIG. 4) In other words, it is recognized that the data has been read normally. first flip-flop 7
When either the output F of the output F or the output H of the third flip-flop 9 is false, the AND gate 11 or the AND gate 13
Since the condition is met, an error (E
R) is recognized as an abnormal reading. That is, even if the read signal A falls before the first clock B due to some factor such as the timing of the third data in FIG. 4, the second flip-flop 8 retains that the read signal A has been generated. Ori.

The first clock B looks at the read signal A and resets the first flip-flop 7, and the second clock E looks at the output G of the second flip-flop 8, which is set and held by the read signal A. Set the third flip-flop 9. That is, when the check timing K is issued, the output F of the first flip-flop 7 is false and the output H of the third flip-flop 9 is true, so the condition of the AND gate 11 is satisfied and an error ( E.R.
), a signal is issued and it is recognized as an abnormal reading, so data continues to drop. It is possible to prevent abnormal conditions that should not occur.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to dramatically improve the reliability of read information with a relatively simple circuit configuration.

Further, abnormal reading conditions caused by noise or the like can also be detected as errors, making the margins very tight.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional reading circuit, and FIG. 2 is a time chart of the conventional reading circuit. FIG. 3 is a circuit diagram of a reading circuit in one embodiment of the present invention, and FIG. 4 is a time chart of one embodiment of the present invention. 7...at flip-flop. 8...Second flip-flop. 9...Third flip-flop. to, II, 13...and gate. 12...Orgate.

Claims (1)

[Claims] In a reading circuit for data recognition in a card reading device, a first flip-flop receives a read signal using a first clock and is reset after recognizing the data, and a first flip-flop is set by the read signal and reset after recognizing the data. a second flip-flop that receives the output signal of the second flip-flop using a second clock that is generated later than the first clock, and a third flip-flop that is reset after recognizing the data; , a circuit for comparing and collating the output signals of the first flip-flop and the third flip-flop.